Part Number: ADS7867
Dear Technical Support Team,
Why does ADS7867 have the difference of tc(sclk) between high VDD and Low VDD?
Does ADS7867 have unusual architecture?
Datasheet shows that the higher VDD is, the lower tc(sclk) is.
Our customer'd like to use much larger than 6.7us with 3V , if possible.
In other word , more slower frequency(Hz) than datasheet spec of tc(sclk).
Typical ADC doesn't have maximum tc(sclk) spec, but this device have them and the limitation depending on VDD.
In reply to Evan Sawyer:
In reply to ttd:
Hi Evan Sawyer,
Thank you for your reply.How come it that the speed is limited?For example, is there the limitation to keep the accuracy on datasheet like gain error?
ADS7041 seems to be much easier to use sclk than ADS7867.
Thank you for your suggestion.
Hi Evan Sawyer, Thank you for your reply. Why are min and max value of "tDIS(EOC-SDOZ): Disable time" related to max 6.7μs"tc(sclk): Cycle time" ? I didn't understand these relationship.
I'd like to know what happens when tc(sclk) is over max 6.7μs.
I guess that leak current of sample & hold circuit with 3V is larger than leak current of low VDD, so sclk can't be slow with 3V VDD.
Best Regards, ttd
Hi Evan Sawyer, Thank you for your reply. I was relieved to hear that user can use SCLK between 10 kHz and 3.4 MHz above 2.5V without performance degradation. It makes customer's development easy. You commented that the datasheet uses the specifications 'tc(sclk): μs' and 'frequency of sclk: Hz' interchangeably which is misleading. Do you have a plan to fix datasheet? Best Regards, ttd
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