I have a problem using ads1232,
only SCLK , DOUT/DRDY connected through series FerriteBead(200_ohm@100MHZ) to Micro,( two 27pf caps from those pins to GND are added in ads1232 side as low pass filter for UHF and GHZ noises )
the /PDWN is connected to external reset circuitry that have voltage between 4.0 to 5.0 volts,( one 1k series resistor and 27pf cap exist here as LowPass filter )
it has a 500ms delay after powering up the digital and analog sections (pulls down the /PDWN pin) thus it is enough for initial reset of ads1232 !
the gain is set to 128 , speed for 10SPS , TEMP = 0 , A0 = 0 , AVDD = 5.0 , DVDD = 5.0 from different REGs , AGND , DGND are connected in one point near the main CAP of POWER ;
it works fine in the most of times, it has peak to peak noise in my system ( +- 30 ) nearly twice the ti_pdf mentioned, and I have stable readong of 60/8,000,000 = 133,000 counts , this is enough for my system.
the problem is here:
some times after powerup or in normal operation , the reading of a2d if shifted by -8500 ( eg: from 139,500 it jumps down to 131,000 )
( or from 310,000 it jumps down to 301,500 )
but the gain is satble..
and this unwanted huge offset will remain until :
1. turn off then turn on the system , sometimes removes the offset
2. manually pulling down the /PDWN to gnd by a wire! ( every time this will remove the offset temporarily , but the problem may occure some minutes later!)
3. using the 26 clock for internal offset calibration,( every time this will remove the offset temporarily , but the problem may occure some minutes later!)
because of unpredictable occurance of this issue , the system is unreliable,
what is the source of this ( internal offset registers UNcalibrator ) ????
what changes should I do for solving the problem?
notes on FerriteBead and cap
( I think the 27pf cap connected to ads1232 pins are small enough to have no effects in loading and changing characteristics of ads1232 )
( the FerriteBead(150nH) and 27pf cap make 82MHz corner frequency for LowPass filter for reducing EMI noises from Digital cpu side to analog side )
You are correct about the common mode input range being violated if indeed you were trying to measure the inputs. The reference design you are referring to does not ever read the AIN2 inputs, and thus the mux is never connected to the PGA. It is always a good idea to connect floating inputs to something. Usually the easiest place to connect is ground.
There is a lot of information to digest from your latest post. Let me try to make a couple of points clear. The first is that all delta-sigma parts have issues with offset from the modulator that needs to be calibrated out. You should always run the offset cal and this should be your baseline measurement.
Also, it would appear that you have some grounding issues. It is always a good idea to join the grounds for the analog and digital portion very close (even under) the device (ADS1232.) Long ground traces are not a good idea. Nor is it a good idea to use an inductance of any type to bridge the grounds together. We have found that a single ground plane works very well as long as the analog and digital portions are not crossing over each other.
The device is sensitive because it is designed to be sensitive. A very high input impedance will respond to a very small charge.
Did you ever place the caps at the supply pins for bypassing as well as a bulk capacitor across the reference? Without these caps you will never get the performance you desire.
The PCB includes 0.1uf ML cap for DVDD,DGND (Cs5) Close to pins1,2
and 0.1uf ML cap for AVDD,AGND (Cs6) Close to pins 17,18 plus a 100uF electrolite cap ( CEA2 )
and new questions:
?7? . What does happen , when the AVDD has delay after DVDD becomes stable at 5.0 volts ( a delay of 1 sec ) or vice versa?
?8?. What does the device do when we insert extra 27th and 28th and... SCLK immidiately after 26th SCLK ( without waiting for complition of internal operations ) ?
?9?. what does happen if some tracks routed under the chip body on the PCB( such as my case ) ?
?10?. what are the behaviors of the device , when it is damaged by:
- Over heating in soldering process by iron tip ?
- Static Electricity of Body , in manual assembly ?
?11?. In which conditions do I consider the device is damaged ?
At this point I'm not going to answer all of your questions because I think the real answer will get lost. You have a serious analog issue that starts at the input. First of all the regulator you are using has noise issues of about 200 micro-volts or more. This will affect the stability of your readings. However, the bigger issue is your analog ground.
Basically you have one big antenna ground loop. Notice the green trace I have shown on the top layer. Ground traces are bad. You should have a ground plane. I think you you may have thought you have a ground plane because you have large copper areas. Many of these copper areas are either not connected, connected through narrow traces, are in areas not vital to the ADS1232 itself.
Notice the long ground trace to the regulator ground. The regulator ground path should be as close to the power entry point as possible, and capable of handling large currents. Remember you are regulating 8.5V to 5V. Also, the analog bulk capacitor ground has the same issue. All currents end up going right past the ADS1232 ground.
Another thing to consider is the ferrite on the analog ground will choke high frequency noise, and that noise is also passed around the current ground trace that will affect stability and noise of the ADC reading.
If you look at the bottom view of your layout, that I have attached drawn on, you can see how you can make a huge improvement in the analog ground.
This is a start, but you still have a lot of other issues, including the digital ground, and the ground antenna loop around the crystal.
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