ADS1298 + MSP430BT5190

What exactly is the problem you're having?

The problem is that so far I could not do any shows with ads1298, not that I'm failing. I do not get any data in the buffer.

El problema es que hasta el momento no he podido realizar ninguna muestra con el ads1298, no se en que estoy fallando. No obtengo ningun dato en el buffer.

Is this with an ADS1298 evaluation module or your own design? Is the MSP430 on an evaluation board? If this is a pair of EVMs please share how the EVMs are connected, if it's your own hardware please share a schematic. Have you verified the functionality of your serial communication lines with an oscilloscope?

It is my own design, and now I am not in position to use an oscilloscope, you could say I'm working with nails.

Es mi propio diseño, y actualmente no me encuentro en posicion de poder utilizar un osciloscopio, se podria decir que estoy trabajando con las uñas.

Juan,

Your schematic did not post, if you can post it as a PDF I think we'll have better success.

In reviewing your C code I noticed a few things...

#include "msp430bt5190.h"

#define   PWDN             BIT2
#define   RESET_ADS        BIT3
#define   START            BIT5
#define   CS               BIT6
#define   CLKSEL           BIT0

char  RESA[26];
unsigned int i;

void main(void)
{
 
  WDTCTL = WDTPW+WDTHOLD;                    // Stop watchdog timer
  P4DIR = RESET_ADS + START + PWDN + CLKSEL; // P for RESET_ADS, START, PWDN, CLKSEL
  P3DIR = CS;                                // P for  CS
  P4SEL = 0X80;                              //DRDY
 
  P3SEL |= 0x31;                            // P3.5,4,0 option select spi
  P3OUT |= ~CS;                             // Disable CS
  UCA0CTL1 |= UCSWRST;                      // **Put state machine in reset**
  UCA0CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB;    // 3-pin, 8-bit SPI master
                                            // Clock polarity high, MSB
  UCA0CTL1 |= UCSSEL_2;                     // SMCLK
  UCA0BR0 = 0x02;                           // /2
  UCA0BR1 = 0;                              //
  UCA0MCTL = 0;                             // No modulation
  UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
  UCA0IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt

  P4OUT &= ~START;
  //__delay_cycles(100);                    // Wait for slave to initialize
  P4OUT |= ~PWDN;
  //__delay_cycles(100);                    // Wait for slave to initialize
  P4OUT |= ~RESET_ADS;
  __delay_cycles(100);                      // Wait for slave to initialize
  P4OUT &= CLKSEL;                          // Set CLKSEL Pin = 1
  P3OUT &= CS;                              // Enable CS
 

<...begin utilizing the device...>

You've defined the symbol CS as BIT6 from the msp430 header, which is usually defined as 0x0040. In the code above you...

1. Set pin 6 of port 3 as an output
2. Set P3OUT = P3OUT | ~0x0040, which should yield P3OUT = 0x00BF - pin 6 is low
3. Set P3OUT = P3OUT & CS, which will yield P3OUT = 0x0000 - pin 6 is still low

On port 4 you do something similar...

1. P4OUT = P4OUT & CLKSEL - this does not set CLKSEL = 1 unless your code is misleading - I can't tell which port/pin CLKSEL is actually connected to since your schematic did not post cleanly.

These type of assignments make me skeptical of the entire initialization sequence. You should really try to get access to an oscilloscope or logic port or SOMETHING to see what is actually happening on the MSP430 serial lines.

Check out this code on our design notes page. This might help you get things ironed out and set-up.

Usually, I document a little more, but as I do to raise the spi clock to 2 MHz ?

Listo, ya me documente un poco mas, pero como le hago para subir el spi clock a 2Mhz?

This is my schematic

yellow = spi clock

blue = drdy

Juan Gilberto said:

Usually, I document a little more, but as I do to raise the spi clock to 2 MHz ?

Listo, ya me documente un poco mas, pero como le hago para subir el spi clock a 2Mhz?

You'll have to pardon me, but I'm not sure what you're asking. Are you asking if a 2MHz SPI clock is allowable for the ADS1298? Are you asking if your MSP430 can implement a 2MHz SPI clock? Are you asking how to do it?

From your scope shot it doesn't seem like you're achieving any output on the SCLK line...

Hello again.

I think and misconstrued my question, I could make the spi clock operated at 2 MHz and ads like the picture shows drdy starts but stops spiclock.

Hola nuevamente.

Creo que e planteado mal mi pregunta, ya pude hacer que el spi clock  funcionara a 2 Mhz y el ads como en la imagen muestra inicia el drdy pero spiclock se detiene.

The DRDY pulse stops your SCLK? Your MSP430 should be providing the clock to the ADS1298 - the ADS1298 cannot operate as a SPI master and provide the clock. Do you have an ICDI available to step through and debug your code to see what is causing the SCLK to stop?

Sorry for my ignorance........ ICDI?

I'm working with:
-MSP-EXP430F5438
-MSP-FET430UIF

ICDI is an In Circuit Debugger Interface. The MSP-FET should be the ICDI for your device. You might set a break point in the ISR servicing the DRDY interrupt and see what is happening to your SCLK line.

Do not think of any interruption in the isr.
the voltage supply:
ads1298 = -1.5/1.5 and 1.8 volts
msp430 = 3 volt

the voltage reaches drdy is 1.2 volts

Hello again.

So far, I could not get data from the ads, these are my SCLK signals (yellow) and drdy (blue) that I'm failing.

Thank you for your help.

Hola nuevamente.

Hasta el momento, no he podido obtener datos del ads, estas son mis señales de sclk (amarillo) y drdy (azul) en que estoy fallando.

Gracias por su ayuda

#include "msp430x54xA.h"
#include "hal_pmm.c"
#define   PWDN             BIT2
#define   RESET_ADS        BIT3
#define   START            BIT5
#define   CS               BIT6
#define   CLKSEL           BIT0

char  RESA[27];
unsigned int i;

void main(void)
{
 
  WDTCTL = WDTPW+WDTHOLD;                   // Stop watchdog timer
 
//------------------------------------------------------------------------------
SetVCore(PMMCOREV_1);                     // Set VCore = 1.6V for 12MHz clock
  P1DIR |= BIT0;                                        // P1.0 output
  P11DIR |= 0x07;                                     // ACLK, MCLK, SMCLK set out to pins
  P11SEL |= 0x07;                                      // P11.0,1,2 for debugging purposes.

  UCSCTL3 |= SELREF_2;                      // Set DCO FLL reference = REFO
  UCSCTL4 |= SELA_2;                           // Set ACLK = REFO

  __bis_SR_register(SCG0);                  // Disable the FLL control loop
  UCSCTL0 = 0x0000;                                 // Set lowest possible DCOx, MODx
  UCSCTL1 = DCORSEL_5;                      // Select DCO range 4MHz operation
  UCSCTL2 = FLLD_1 + 122;                   // Set DCO Multiplier for 4MHz
                                                                      // (N + 1) * FLLRef = Fdco
                                                                     // (122 + 1) * 32768 = 4MHz
                                                                      // Set FLL Div = fDCOCLK/2
  __bic_SR_register(SCG0);                  // Enable the FLL control loop

  // Worst-case settling time for the DCO when the DCO range bits have been
  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
  // UG for optimization.
  // 32 x 32 x 4 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
  __delay_cycles(125000);
    
  // Loop until XT1,XT2 & DCO fault flag is cleared
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
//------------------------------------------------------------------------------  
  P4DIR |= RESET_ADS | START | PWDN | CLKSEL; // P for RESET_ADS, START, PWDN, CLKSEL
  P3DIR |= CS;                               // P for  CS
  P4OUT = 0;
  P3OUT = 0;
//------------------------------------------------------------------------------
  P1DIR |= 0x01;                            // Set P1.0 to output direction
  //P1REN |= 0x80;                            // Enable P1.4 internal resistance
  P1OUT |= 0x80;                            // Set P1.4 as pull-Up resistance
  P1IE |= 0x80;                             // P1.4 interrupt enabled
  P1IES |= 0x80;                            // P1.4 Hi/Lo edge
  P1IFG &= ~0x80;                           // P1.4 IFG cleared
//------------------------------------------------------------------------------  
  P3SEL |= 0x31;                            // P3.5,4,0 option select spi
  //
  UCA0CTL1 |= UCSWRST;                      // **Put state machine in reset**
  UCA0CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB;    // 3-pin, 8-bit SPI master
                                            // Clock polarity high, MSB
  UCA0CTL1 |= UCSSEL_2;                     // SMCLK
  UCA0BR0 = 0x02;                           // /2
  UCA0BR1 = 0;                              //
  UCA0MCTL = 0;                             // No modulation
  UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
  UCA0IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt
//------------------------------------------------------------------------------
  P5SEL = 0xC0;                             // P3.4,5 = USCI_A1 TXD/RXD
  UCA1CTL1 |= UCSWRST;                      // **Put state machine in reset**
  UCA1CTL1 |= UCSSEL_2;                     // SMCLK
  UCA1BR0 = 35;                              // 4MHz 115200
  UCA1BR1 = 0;                              // 4MHz 115200
  UCA1MCTL |= UCBRS_1 + UCBRF_0;            // Modulation UCBRSx=1, UCBRFx=0
  UCA1CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
  UCA1IE |= UCRXIE + UCTXIE ;               // Enable USCI_A1 RX interrupt
//-------------------------------------------------------------------------------  
  //P1OUT &= ~0x02;                           // Now with SPI signals initialized,
  //P1OUT |= 0x02;                            // reset slave

  P3OUT |= CS;                              // Enable CS
  P4OUT |= PWDN;
  P4OUT |= CLKSEL;                          // Set CLKSEL Pin = 1
 
 
  P4OUT |= RESET_ADS;
  __delay_cycles(4000000);                      // Wait for slave to initialize
  P4OUT &= ~RESET_ADS;
  __delay_cycles(4000000);                      // Wait for slave to initialize
  P4OUT |= RESET_ADS;
  __delay_cycles(4000000);                      // Wait for slave to initialize

  P3OUT &= ~CS;                             // Disable CS
 
//-------------------------------------------------------------------------------
  while (!(UCA0IFG&UCTXIFG));            // SDATAC
  UCA0TXBUF = 0x11;
  __delay_cycles(100);
 
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x41);               // WREG Escribir registros a partir de la dirección 01
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x18);           // Escribir registros
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x06);               // CONFIG1
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x30);               // CONFIG2
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0xDE);               // CONFIG3 0XDE Referencia de 2,4V; 0xFE Referencia de 4V
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0xF3);               // LOFF
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // CHnSET1   DI                     
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // CHnSET2   DII    
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // CHnSET3   V1
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // CHnSET4   V2
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // CHnSET5   V3
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // CHnSET6   V4
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0X00);               // CHnSET7   V5
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // CHnSET8   V6
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x03);               // RLD_SENSP
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x01);               // RLD_SENSN
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0xFF);               // LOFF_SENSP
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0xFF);               // LOFF_SENSN
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // LOFF_FLIP  (Solo lectura)
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // LOFF_STATP (Solo lectura)
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // LOFF_STATN (Solo lectura)
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // GPIO
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // PACE
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x00);               // RESP
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x02);               // CONFIG4
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0x08);               // WCT1
  while (!(UCA0IFG&UCTXIFG));            
      UCA0TXBUF = (0xCA);               // WCT2        
 
 
  while (!(UCA0IFG&UCTXIFG));            // RDATAC
  UCA0TXBUF = 0x10;
 
  P4OUT |= START;
//------------------------------------------------------------------------------
  __bis_SR_register(LPM0_bits + GIE);       // CPU off, enable interrupts
}

#pragma vector=USCI_A1_VECTOR
__interrupt void USCI_A1_ISR(void)
{
  switch(__even_in_range(UCA1IV,4))
   {
    case 0:break;                             // Vector 0 - no interrupt
    case 2:    
      if(UCA1RXBUF==1){
        P1OUT |= 0X01;
      }if(UCA1RXBUF==0){
        P1OUT |= 0X02;
      }
        

    break;
    case 4:break;                             // Vector 4 - TXIFG
    default: break;
  }
}

#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
  switch(__even_in_range(UCA0IV,4))
  {
    case 0: break;                          // Vector 0 - no interrupt
    case 2:                                 // Vector 2 - RXIFG
      while (!(UCA0IFG&UCTXIFG));           // USCI_A0 TX buffer ready?

  while((P1IN & 0x80));
 
   for (i = 0; i < 27; i++)               // Read Channel data
   {
    while (!(UCA0IFG&UCTXIFG));
    UCA0TXBUF = 0x00;
 
    while (!(UCA0IFG&UCRXIFG));
    RESA[i] = UCA0RXBUF;
   }
      
   while (!(UCA0IFG&UCTXIFG));           // USCI_A0 TX buffer ready?
   UCA0TXBUF = 0;                 // Send next value

    break;
    case 4: break;                          // Vector 4 - TXIFG
    default: break;
  }
}