I can not make out when is the output data valid from the t_DHLD and t_ACC timing description.
The ADC serial output data is valid after SCLK goes low and only holds for 11nS min per t_DHLD parameter or is available, has access for 27nS max per t_ACC.
Is the t_DHLD 11nS min a delay or is the data valid right after SCLK goes low?
Is T_DACC a delay ?
Robert Illan
256 489 5200
Hi Robert,
Welcome to the e2e Forum! Can you tell us which version of the ADC128S series devices you are looking at specifically? Is it the ADS128S022, ADS128S052 or the ADS128S102?
Regards,
Tom
I agree, the diagrams we have provided are difficult to make out... but the information is there and is valid.
Say the DOUT is actually an output of a D-Flip-Flop, and this D-FF is clocked by the falling edge of the SCLK.
TDHLD is the time that the "old" state will persist at the output of D-FF after the falling edge of the SCLK.
TDACC is the time when the new data will reach the valid level at the output of D-FF.
As an example: prior to the arrival of the falling edge of SCLK the output of D-FF was LOW. Then the data at the input of D-FF changes to HIGH. Then the falling edge of SCLK arrives.
The LOW will persist at the output of D-FF for the length of TDHLD, then the output of D-FF will start rising to a new HIGH level and reach valid level after TDACC interval after falling edge of SCLK.
Hope this answers your question. If not, please let me know.
Sincerely,
tom
Thanks for the explanation, the old data is valid before the falling clock an 11nS min after the falling clock. New data is valid 27nS max after the falling clock. Like you said the information is there but not in terms of DataValid.
For the max clock is 16 MHz, 62nS period, then DataValid has a setup time of 35nS min before the falling clock.
I am using the ADC128S102.
HI Robert,
That is correct: with SCLK period of 62ns, we are "ADC gives you" minimum of 35ns of set-up time.
Cheers!