I have problem in undemanding theory of using oversampling to increase ADC resolution.
Consider ADS8320 as convertor with 2.5 reference i expect to have 38uV/bit resolution. Imagine that I oversampled at 12800 sps
to achieve final 50sps, I expect 4 bit improvement which means 2.4uV/bit. Now I imagine a sin signal with amplitude of 38uVpp.
I expect count 16 at V peak but while ADC output always remain at zero count how can I take signal out of all zero counts samples!?
Alireza TaghizadehI expect count 16 at V peak but while ADC output always remain at zero count how can I take signal out of all zero counts samples!?
You cant. To implement something like this you need to modify your ADC reference or gain up the 38uV signal. Right now you're more or less oversampling a 0 bit signal since your input is so small that you cannot detect it. To really take advantage of oversampling you should be using the full resolution (or at least a few hundred codes) of your front end first.
Converting a 38uVpp sinusoidal waveform with a 16 bit ADC is quite the lofty goal without filtering or applying some gain to the signal.
You might look at a converter that has more bits to start with and perhaps some internal PGA settings to help you gain up the signal. We have a number of offerings in this area.
-------------------------------------- Kevin Duke Precision DAC Applications
Thank you Kevin.
I have already found partial answer to my question in the following document:
Decreasing reference voltage is not my solution since I want to to increase dynamic range by oversampling.
What I was missing was use of additive signal, though implementation of such approach is a great challenge for me!
I am still looking for more detailed documents on this.
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