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Precision Data Converters Forum
DAC1220 communication problem
I'm working with the DAC1220 and a third party processor. I designed a board with a DAC1220 configured for 20 bits operation.
So, everything seemed to be okay but my customer says the output is not always "correct".
After investigating this issue, I discovered something strange. I ran a test program that tries all output codes, one after one and at the same time on several DAC1220. Sometimes (randomly), I can see 3 different types of "wrong" outputs:- the output ranges from 2.5V to 5V instead of 0V to 5V;- the output ranges from 0V to 5V but with "strange" pattern;- the output doesn't changes anymore.
I used a logic analyzer to check SPI data and I didn't find any error. Same data for all DAC1220. SPI is running in mode 1 at 190kbits/s.New output code is sent every 2 ms. DAC1220 is operating from a 2.4576MHz crystal and the board was designed along the lines of the EVM.
Applying a reset pattern solve the problem temporarily but is not acceptable as the DAC1220 is used in a servo loop.
After spending hours to find where is the problem, I would like to know if someone can give me some advices.I can give more details if needed.
Is it possible to get a screen capture of the SPI communications to your DAC1220? This sounds like there may be some corruption in the data or SCLK. Is it possible as well to get a copy of your schematic showing how you've connected the DAC1220 to your host processor?
Were you able to achieve any success in resolving your issues? If not, can you send us the information Tom requested? Also, it would be good to know the commands that you are giving to initialize the device.
Sorry for late reply, these days were off in France.
The system is inside a 19" rack.
So, I attached the schematic of the DAC1220 board. I didn't put the processor part as it's only wires from SCLK, MOSI, MISO and CS to the backplane.The backplane is a part from Schroff (Pentair).Power supplies are also from Shroff. These are linear power supplies, one 5V for the processor side and 15V for the DAC side. Digital power supply for the communication side of the DAC is made from the 15V.
The other attachement is a screen catpure of the communication when outputs were "wrong", with VCD and open logic sniffer files.
What value are you writing to the CMR register and how often are you writing the register? The issue seems to be a change in the value to the CMR. If the value doesn't change, then the device appears to be in sleep mode. If the value only appears to be half range, then perhaps it is configured in offset two's complement instead of straight binary.
Might there be something in the code that might be accidentally re-writing the CMR to the device?
In my test process, I write all binary codes, one after one from 0x00000 to 0xFFFFF and every 2 ms.
I already checked about CMR. My code is simple : init in main and new DIR values in an timer interruption. CMR is accessed only in main.
Yesterday, I modified the code to be able to dump all registers from the DAC to understand what is happening. This morning, the output of one DAC is fixed (2.5V) and I can see that the SPI communication stopped working.I get the same answer for all register reads (I attached a screen of the communication for one register).
Edit : I checked the clock : stable at 2.45MHz. I noticed that when the output is "wrong", all registers reads are 0xFFFF(FF) (is this is what we can see on the attached screenshot).
I think this may be related to power and/or ESD/EMI/RFI. I would first suspect the grounds. It is vital that AGND and DGND of the DAC1220 not be more than 300mV apart. This can be a problem if there is inductance between the grounds. This is often overlooked as you can have a good DC path, but fast rise time noise can create large voltage differences with path inductance. The inductance can be from devices or even traces. I've seen long traces between AGND and DGND become problematic. If you want to send me your layout, I can look it over for any potential issues.
It is also hard to tell where you have your cap placement. Bypass caps should be close to the DAC1220 and effectively routed.
Another possibility is issues with isolators. This sometimes can be a problem if the signals have a disturbance from noise. One side can look clean while the other may not be as clean. Clocks can sometimes double trigger.
I also suspected an EMI/RFI issue yesterday. So, I ran a test without anything connected to the output (before, there was an oscilloscope). And after maybe 10 hours, the software can read correctly all registers.
If you look at the board design, you can see a choke on the power ligne, but DGND is connected before this choke. There is also a schottky beetween DVCC and AVCC, near the DAC1220.So, I understand the problem but I don't know how to solve it. Removing the choke can be a solution but I added it because of the noise on the output.Can you give some advices about this ?
I attached gerber files and PCB design software screenshot to show you the layout. You can notice that there is a frame over the DAC1220. The board is placed inside an EMI/RFI box... inside an EMI/RFI rack.
This is one of those difficult cases where the ground return path for the digital supply is being forced through the substrate of the device. I have some PCB grounding info that was written primarily for ADCs, but is also true for DACs. That information can be found in the Design Notes:
I'm not sure how easily this can be fixed. You could add a top area plane for the digital ground around the digital portion of the DAC and then use a much wider track instead of the narrow track to the main digital ground plane. I would also suggest you use a much larger via, or better yet, a series of vias to connect the ground trace to the ground plane. It is really much better to connect the ground of the DAC together near the part, but you may be able to make it work by removing as much inductance as possible with your current design. The current layout really doesn't have a good digital ground so that is a good starting point. The key is removing as much inductance as possible from between the grounds so that they don't separate at the device by more than 300mV.
According to what you explained, I decided to shortcut the ground side of the choke to avoid voltage difference beetween AGND and DGND.After more than 100 hours of test, I can say this issue is solved. Maybe I will modify the layout for future release.
Thanks for your support.
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