The noise is a broad hump (5kHz – 10kHz wide) that is 6dB to 10dB above the noise floor. Its frequency changes with sample rate and sometimes over time. I have changed the analog power supply, reference and input and it remains. I cannot see it on the reference, power supply or inputs in-band with an audio spectrum analyzer (it may be high frequency aliasing down). I have put an anti-alias filter at 40kHz on the input and it is still there. I have the board in a shielded box and have turned off the Wi-Fi and other RF transmitters in the building with no luck.
We are using the internal clock for sampling, and manual trigger mode. We are not reading in the quiet time.
Using the EOC/INT/CDI pin as EOC, active low output, there is approximately 20ns of jitter on the rising edge of the EOC line relative to the start of conversion. The EOC line is low for what should be 18 CCLKs based on the data sheet numbers, but the duration has the 20ns of jitter. This leads me to think the internal clock has jitter and could be causing the noise.
I am wondering if the jitter is normal. Also, could the internal clock be beating with the SPI clock and data and causing noise internal to the device? At most sample rates we are not reading during the concersion, so I do not think beating is the issue.
Welcome to our forum! I don't recall seeing this behavior in the ADS8329. Can you let us know how you have the configuration register (CFR) set and possibly share a snippet of your schematic with us? We can try to repeat your tests here. What reference are you using?
Attached is a copy of the schematic for the ADS8329 section. There is an error on the schematic showing a 27pF capacitor on the 1.8V power line, it has been replaced with a 4.7uF capacitor.
The analog switches for the filter and the gain at the input buffer (U156, U159, U60) have been removed. R376 has been populated with a 0 ohm resistor, and R53 removed (U155A is a unity gain buffer with a first order anti-alias RC filter on its input).
So to simplify, the signal is connected from C211 (AC_IN) to R316 (HSIN) and the output of U155A is connected to R143 (HS_ADC_IN). The input side of C211 (IN) is shorted to analog ground.
The reference is MAX6145.
Manual channel selection mode
Internal conversion clock used
Manual trigger manually started by falling edge of CONVST
EOC active high / INT active low
Pin 10 used as EOC
Pin 10 used as EOC/INT output
Auto nap power-down disabled
Remove device from nap power-down (resume)
Remove device from deep power-down (resume)
TAG bit disabled
The data sheet shows a 470pF capacitor between pins 3 and 4. The pole formed with the 20ohm resistors is well out of band. Is there any drawback to increasing the capacitor value? I notice the noise floor drops with a larger (10nF) capacitor.
Has this issue been resolved? I know you were working off-line a bit with Ryan with this issue but I've not heard anything from him lately.
I still have not found a solution or cause. I am looking at sending a blank board so the factory guys can try to replicate the problem.
Great! Work through Ryan and we'll see what we can do on our end.
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