I am working on ADS1278 which is having 8 analog and digital channels. Schematic setup is explained below.
Schematic Setup :
I have connected SYNC, FSYNC , SCLK, CLKDIV, DOUT1 signals. I want to operate the 1278 IC in Low speed mode and CLKDIV made as 1(High) also mode pins set to "11" . FORMAT(2:0) pins are set to "100". So i have set Frame_Sync Format. I have given 27MHz crystal clock to the ADC.
Software(Programming in FPGA): All the below operation is happening on falling edge of the 27Mhz clock.
By default SYNC is high, then it made it as low for one clock cycle (It will go for high '1' after 1 clock cycle). FSYNC is generated continuously for 128 conversion cycles.
After that i generated FSYNC (Made high for one clock cycle and made low). Data is collected for next 24 clock cycles then waited for 2535 clock cycles. Again process(FSYNC generation and data collecting) is continuously running. I have seen varying analog input. But digital output i am not able to see on the scope (at DOUT).
Can you please take me forward?
Could you send a scope picture showing your Frame Sync line, SCLK, data, etc. I would recommend getting your hands on an EVM so you can look at the timing of our communication. The EVM-PDK evaluation software uses the Frame Sync protocol so you can look at it on a scope to hopefully help debug.
1278 is not responding in my design. I have changed Frame_Sync format to SPI format, just to check DRDY on the DRDY/FSYNC pin. But DRDY is continuously high. It's not pulsing only. I have kept SCLK to '0'. I kept high on PWRDN1 and PWRDN2 pins as well. I am not able to understand why ADC is not giving the DRDY?
If placed in SPI mode, you should see the /DRDY line idle high and pulse low at the data rate frequency. If you are not seeing these /DRDY pulses, which are approximately 4 tclks (master clock periods), then the device is either in a power down state or it is not getting a master clock. Double check that the ADC is being fed a master clock user for all the ADC internal timings and conversions. If the master clock is there, double check that, at least, one of the power down pins is held high so the device is not put to sleep. If that is correct, double check the supply pins to make sure the device is properly powered. When configured correctly, you should, at the very least, be able to see the /DRDY pin toggling. If connected to the FPGA, make sure that the I/O pin is set to an input so that the FPGA is not driving the /DRDY line high or low as the converter tries to toggle it.
Master clock is going to ADC & CH1, CH2 channels (PWRDN1, PWRDN2) are held high. All the mentioned voltages are given to the respective power pins (5v, 3.3v, 1.8v) and DRDY pin made as input to FPGA. But DRDY is continuously high only. I don't know the reason. I have done one mistake. That i explained below.
When changing Frame_Sync mode to SPI mode i have done one mistake. In Frame_Sync mode DRDY/FSYNC made as output i.e FPGA wa driving the FSYNC. When i changed to SPI mode both are happening(FPGA was driving FSYNC and ADC also try to drive the DRDY line) for some time(2 - 3 min). Then i configured DRDY as input. Do you think is it problem for ADC?
I glad to inform that "i am able to get DRDY from ADC." But i didn't got idea how the DRDY will work? I have attached the video clip of DRDY, SCLK here. DRDY status is changing continuously in each conversion. I am reading 1st channel at DOUT1. I have planned to read the all the channel data on DOUT1 itself. Please see the attached video clip and please give me an idea on DRDY.
/DRDY is used for SPI rather than /FSYNC. I assume you have switched to using SPI now.
/DRDY is an interrupt used to alert the user when new data is ready. A falling edge of /DRDY lets the user know when data is ready. The line will then return high when it sees the first SCLK pulse. If no SCLKs are sent, the /DRDY will remain low until new data is ready, in which it will return high and immediately low. Basically, the line will appear to idle low and pulse high when no SCLKs are sent. I would recommend re-reading the data sheet now if you are now using the SPI communication mode.
Thanks for your valuable reply. After your reply i have gone through the datasheet again and I have observed the changing in DRDY without SCLK and with SCLK. I have seen one channel data (CH1 channel data) on DOUT1 pin.
If i want to read all the channel data i should generate 24 * 8 (SCLK) pulses (24 SCLK for each channel, so total 192 SCLK pulses required to read off all the channel data) and i should read the status of the DOUT1 pin on each rising edge of the SCLK.
This is my understanding after reading datasheet. Please correct me, if my understanding is wrong.
You are correct. Double check your format pins with page 30 of the data sheet to make sure you are in TDM mode with the SPI interface to have all the output data come out of DOUT1.
I have read the serial data from ADC and done serial to parallel data using shift register in FPGA. I have detected DRDY then i have generated SCLK (24 clk pulses to read 24 bit of data) to read the data from ADC. The clock frequency same as Master Clock. Master clock i have used is 27 Mhz. So the SCLK switching frequency also same (27 Mhz for 24 clock). With this case read data is not proper.
When i reduce the master clock to 6.75 MHz read data is proper (SLCK switching frequency also 6.75MHz).I am getting 2.5 KHz data rate with this case.I don't know where the data problem lies.
Can you please help me to increase the data rate?
Double check your timing specs. A lot of time the tMSBPD timing spec is overlooked causing you to miss the MSB offsetting the entire data word. Another place to look is at the SCLK phasing and polarity. What edge are you using to latch data and to change data? If this is incorrect, there could be a chance that the data is read properly at slower speeds and read back as incorrect when run faster. Slowing the master clock down is going to slow the requirements for a lot of the internal timings so, best place to look is the timing diagrams relating SCLK to the master clock to try and see what is not being met. I would look at your SPI transfer word on an oscilloscope to try and see if something may be wrong. If you post a picture of your o-scope data word and SCLK, I would be happy to look.
Here i am attaching 3 videos. They are
1)Wavefroms -- DRDY with SCLK is shown & Data with SCLK is shown. I am reading 4 channels continuously on DOUT1. But only one analog input is connected to CH1 and rest of the analog pins of ADC is kept open.
2)Data_at_6_5Mhz_clk -- Continuous read data is shown in the video while varying the analog voltage across the ADC. Master clock provided here is 6.5Mhz.
3)Data_at_27Mhz_clk -- Continuous read data is shown in the video while varying the analog voltage across the ADC. Master clock provided here is 27Mhz.
I have looked through the videos and see that there is a fair amount of noise on the SPI lines? Is that truly there, or are you not grounding the oscilloscope probe properly. If it really is that noisy, you may want to include series 33 ohm resistors on the SPI lines to try and clean in up. If they are that noisy, that could lead to inaccurate readings on the communication side of things. My recommendation for testing is to put full scale on the input channel during testing. This would allow you to track what you are reading back relative to full scale when sweeping the master clock to help you get an idea of how your data is incorrect. It is hard for me to understand by what factor your data is off when I do not know your input signal amplitude. keep the input constant at either +Vref or -Vref. I would actually recommend railing the input by Vref + 100mV to insure that your 'correct' output reading is always reading 0x7FFFFF.
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