RE: spi double buffer testing in msc1210 y5

Hi Bob,

I'm trying to setup SPI with double bufferred settings with poling, but I'm having difficulty on making it works. After comparing the test package, I found out that you set the FIFO bit of SPICON. However, I read it some of your literature (Revised Nov 2004) and errata warn about not using the FIFO due to unstability. Is that true?

The following is my configurations and function call for transmission (SCK, MISO, MOSI & SS are the P1 bits):

void SPI_Init()
{
  PDCON&=~0x01; // turns on SPI
 //CYCLOPS - Enable SPI channels as master
 P1DDRH=0x75;  //CMOS Out
 //P1DDRH=0xBA;  //Open Drain
 //P1DDRH=0x30;  //Pull Up
 SCK=1;
 MISO=1;
 MOSI=1;
 SS=1;
 SPICON=0xE6; // ClkDiv=111(clk/256), Order=0, MSTR=1, CPHA=1, CPOL=0
 SPITCON=0x28;
}

char SPI_Transmit (char TxData)
{
 while ((AIE&0x08) != 0x08){}
  SPIDATA=TxData;
 while ((AIE&0x04) != 0x04){}
  return(SPIDATA);
}

I've also tried the sample code in the user guide sba077, it is not working as well. Do you have sample code to configure double buffered with poling?

Thanks. 

5 Replies

  • Hi Andrew,

    Unfortunately I'm out of the office on vacation/holiday break.  I'll be back into the office the middle of next week and will get an answer as soon as I can.

    Best regards,

    Bob B

  • In reply to Bob Benjamin:

    Hi Bob,

    Sorry for troubling you on your vacation. I hope you enjoy your holidays!

    Some update for you. I manage to configure the MSC1211 EVM SPI communication (active high/no SS) to work on double buffered polling on every 1 second interrupt, but not to the settings I wish (16 bits per transfer using active low Slave Select pin). My settings are:

     PDCON&=~0x03; // turns on System Timer and SPI
     P1DDRH=0x75; // CMOS output (push pull) for P1.7, P1.5 and P1.4
     SPICON=0x44; // Divide 8, FIFO off, msb, master, CPHA=0 
     SPITCON=0x28; // SCK driver on

    1) As a SPI Master, do I need to manually negate slave select pin for every transfer?

    2) I'm planning to send 2 bytes in one SPI transfer, with manually toggling the SS pin before and after sending 2 bytes.However, it seems that MSC1211 automatically deassert and assert the SS pin after the first byte being sent (tested with CPHA=0 and CPHA=1 and both give the same result). How do I overcome this?

    Thanks and happy new year.

  • In reply to Teik Eng Ewe:

    Hi Andrew,

    Happy New Year to you too!  Typically the SS pin when operating as a master will drive the pin low for every single byte sent.  This is problematic for devices that use multi-byte transactions.  Some micros allow for a larger transaction size, but these are usually related to 16 bit processors and higher.

    One way of getting around this is to use the SS pin as a GPIO (instead of part of the SPI interface) and manually control the pin for transactions that are larger than a byte in size.

    Best regards,

    Bob B

  • In reply to Bob Benjamin:

    Hi Bob,

    Is the Errata #1 in SBAS203A still valid? It is about not recommending the use of FIFO for SPI.

    Rgds,

    Andrew

  • In reply to Teik Eng Ewe:

    Hi Andrew,

    The errata is still valid.  In fact if you look at the current datasheet for the MSC1210 there is not even an option listed for FIFO mode in SPICON register.  This differs from the MSC1211 which has a separate errata for specific lots.

    Best regards,

    Bob B