ADS1243-HT : RREG command : Can I issue the command one time and keep reading out the register value to poll the DDRY bit status?

Yuquan,

There is no ADS1234-HT product.  Did you mean ADS1243-HT?

Best regards,

Bob B

It is ADS1243-HT. My fault

Thanks

Yuquan,

For the ADS1243 you will need to issue the complete RREG command each time you wish to read from the register to poll the DRDY status.

Best regards,

Bob B

Another question :

I believe that for each command, we need to select the chip to start, issue command ..... and de-select the chip to finish the command.  Is this right?

Thanks Bob for the quick response.

Hi Yuquan,

Yes, to communicate with the device the CS pin must be held low for the entire communication transaction.  If CS toggles state, the SPI bus is reset within the ADS1243.

Best regards,

Bob B

Hey Bob:

If I finished one command, can I issue another one without De-select the CS pin  and then select the CS pin ?

( De-select the CS: to finish the first command? and select the CS pin to start the the second one?)

Thanks

Yuquan,

Yes if CS is already low, you can issue another RREG command.  You do not need to pull CS high, then low again.

Best regards,

Bob B

what if I want to change to another Different  command? Do I need to pull CS high and then low in order to start the Different command?

Thanks

Y.L

Hi Yuquan,

You can give other commands as well, but some commands have some timing restrictions.  On page 10 of the ADS1243-HT datasheet there is a t11 time.  This is the time from the end of one command to the beginning of the next.  The actual length of time is shown in the Timing Requirements table.  This timing holds true even if you toggle the state of CS.

It is possible to hold CS low all the time, but this limits the ability to communicate to other devices on the same SPI communication bus.  Also, there is no way to reset the SPI communications state machine without Reset or powering down the device.

Best regards,

Bob B

Thanks Bob.

We are  reading data  many times from the Converter and then do an average for the data read out.

We have to check the status through command, not the pin value.

You answer make me able to this by RDATA command.

There is another command "Read Data Continuous". The data sheet says this command can be stooped by STOPC or RESET command. 

I also want to see if I can use this command to do my job. While within this command ( No STOPC or RESET issued yet), can we use RDATA command to check DDRY and data reading?

so the sequence is: pull CS low-issue Read Data Continuous command-Wait-issue RDATA command to check DDRY- when DDRY is ready, sent three dummy byte through SPI to retrieve the three byte data-wait-issue RDATA command to check DDRY................

Thanks

Y.L

Dear Sir

I have some question for ADS1243=HT

1)      How do I start an A to D conversion? I read the datasheet and I don’t find any information to start A to D conversion.

2)      In the page 22, there is below statement for the DSYNC OPERATION:

“Synchronization can be achieved through the DSYNC command. When the DSYNC command is sent, the digital filter is reset on the edge of the last SCLK of the DSYNC command. The modulator is held in RESET until the next edge of SCLK is detected. Synchronization occurs on the next rising edge of the system clock after the first SCLK following the DSYNC command. ”

Q1: if I don’t send another SPI command after I send a DSYNC command, The modulator does not work and Synchronization does not occurs, in other words, ADS1243-HT does not work if there is not a SPI clock after I send a DSYNC command. Is my understand correct? I read some opinion on the forum, it seems that A to D is started by DSYNC command, if it is true, the datasheet description is wrong, is it right?

3)      In the page 18, there is below statement for self calibration:

“At the completion of calibration, the DRDY signal goes low, indicating the calibration is finished. The first data after calibration should be discarded since it may be corrupt from calibration data remaining in the filter. The second data is always valid”

Q1: What means “The first data after calibration….?”

Q2: Should I read both OCR0, OCR1, OCR2 and FSR0, FSR1, FSR2 before the self calibration is started and then read them again after the self calibration is finished?   or I need read them twice after the self calibration is finished?

Q3: Who use these values? ADS1243-HT or designer?

Clark

Hi Clark,

As long as the ADS1243-HT is powered, has an appropriate clock and the PDWN pin is logic high the converter will be converting.  This can be verified by probing the DRDY pin.  DRDY should be pulsing at the appropriate data rate.

For the DSYNC operation you need to send another command.  The best command to send is the Wakeup command.

DRDY transitions from a high to low state when the conversion has completed.  After a calibration, the first results will be invalid.  When running the device in RDATAC mode, the results are automatically posted to the output register.  If you read these results they will be invalid.  You need to wait until the next DRDY transition before you have valid results.

You do not need to do anything with calibration registers, but you can if you want to if you desire to record and restore a different set of calibration coefficients for each mux input.  Some people find this quicker than running a calibration repeatedly.  The ADS1243-HT will use the values to adjust the conversion results to account for any inherent offset or gain errors.  The result you read from the ADS1243-HT will have the corrected data results.

Best regards,

Bob B

Hi Bob B

Thank you for your response.

1) according to your statement of the start  a A to D. how do I stop a A to D operation? send a SLEEP command?

2) Because SELFCAL consist of both  SELFGCAL and SELFOCAL, Does the RDRY go low twice for the SELFCAL operation?  Do the both SELFGCAL and SELFOCAL

take the same time(two tdata)? or SELFGCAL takes two tdata and SELFOCAL takes one tdata?

3) the datasheet said

"At the completion of calibration, the DRDY signal goes low, indicating the calibration is finished. The first data
after calibration should be discarded since it may be corrupt from calibration data remaining in the filter. The
second data is always valid"

the first data means the data inside DOR0, DOR1, DOR2 or  means the data inside OCR0, OCR1,OCR2/FSR0,FSR1,FSR2,?

Clark

Hi Clark,

To stop converting, you can use the SLEEP command or PWDN the device externally at the device pin.  There can be confusion trying to compare the oversampling converter to a SAR, where the SAR often has a conversion start.  Another area of confusion is when using the commands STOPC and RDATAC.  STOPC doesn't stop converting, but rather stops the automatic posting of the conversion results to the output register.  The opposite command is RDATAC which does place the conversion results to the output register after each conversion cycle is complete.  The benefit of the automatic posting is the command byte saved in the communication process (no need for RDATA to be sent.)

If you issue the SELFCAL, the calibration will do both the offset and gain cal procedures and when they are done will set DRDY low.  It will not go low twice.  The time for each calibration is not the same, so you can't divide the total time in half to get the time of just one calibration.

In the section you quoted from the datasheet, data refers to the conversion results not the calibration registers.

Best regards,

Bob B

Hi Bob

I still have some questions

1)    A to D operation follows below steps with the conditions:

VCC = 3.3V,  Fosc = 2MHZ,  SCLK = 0.5MHZ

AN0 = 0.826V,  AN1 = GND;

Vref+  = 1.12V, Vref-  = GND

Due to I sample data every 6 seconds or more, I do need calibration every time I start A to D conversion.

Start a self calibration:

a) write 0x00 to SETUP register (PAG = 1, burnout sources off)

b) write 0x40 to ACR register (buffer disable, range = 0)

c) write 0x01 to MUX register (AN0 is positive and AN1 is negative)

d) send DSYNC command (0xFC)

e) send SLEFCAL command (0xF0)

f) delay 100ms

g) waiting for if DRDY = high

h) read DOR0,DOR1,DOR2 if DRDY = low

Start A to D conversion:

i) write 0x00 to SETUP register (PAG = 1, burnout sources off)

j) write 0x40 to ACR register (buffer disable, range = 0)

k) write 0x01 to MUX register (AN0 is positive and AN1 is negative)

l) send DSYNC command (0xFC)

m) send WAKEUP command (0xFB)

n) delay 100ms

• o) waiting for if DRDY is = high

p) read DOR0, DOR1, DOR2 if DRDY= low

Q1:  Do I need the step: d) h) for the self calibration?

Q2:  if I don’t change the anything of the SETUP, ACR, MUX registers after the calibration finished, which steps can be deleted from i) to p) ?

Q3: I got very strange results below every time I started:

0x575757

0xAEAEAE

0x060605

0x5D5D5C

0xB4B4B3

What is it wrong my code? Is it very critical of the sequence?

2)   The datasheet said “with a PGA of 1 on a 5-V full-scale signal, the A/D converter can resolve down to 1 μV”.

Could you show me how to get 1uV?

3)   There are four SPI modes, which mode the ADS1243-HT supports? Mode0, mode1, mode2, mode3? I can write & read all registers when fosc = 2Mhz/SCLK = 0.5Mhz; but I was failed to write & read all registers when fosc = 4Mhz/SCLK = 0.5Mhz. Could you have some suggestions?

Clark

Hi Clark,

For Q1, no you do not need to issue a DSYNC or read the data following the SELFCAL. 

Q2, if you don't change any settings, the next conversion result should be valid.  You do not need to send DSYNC, WAKEUP.  So you just need to wait the appropriate amount of time until the next result is available.

Q3, it would seem that you are not really storing the correct values when capturing results from the buffer.  Using an oscilloscope or logic analyzer, you should be able to compare the results being sent from the ADS1243 to the results you are storing.  When capturing your data you should retrieve the input buffer contents, left shift the data stored by 8 and add the next buffer contents, etc..

The statement regarding resolving to 1uV is a bit confusing.  The converter resolution is relative to the full-scale range (based on the reference voltage used) and PGA setting.  The ADS1243 full-scale range can also be altered further by the RANGE setting.  One LSB (or one code) is the full scale range divided by the number of bits (2^24-1) for Range 0.

The ADS1243 only supports SPI mode 1.  SCLK idles low and data holds valid on falling edge of SCLK.  If you have communication problems at higher fosc frequencies, then there is usually a problem related to layout or ground stability.

Best regards,

Bob B

Hi Bob

does It work when I send a RESET command or write a register during  the PWDN(pin4) is low?

Thank you

Clark

Hi Clark,

The PWDN pin when low shuts down the analog and digital circuits, so SPI commands sent will not be recognized.

Best regards,

Bob B

"For the DSYNC operation you need to send another command."

Can I send a dummy number/( Sending clock)  through SPI right  after ( I mean no delay in between) sending DSYNC command to make Sync work?

I seems working .

Thanks

Hello:

After we set up MUX, ACR, etc with new value.  Can we just poll DDRY to get data? How do we know that the data we get is done based on our new setting?

Do we need to issue DSYNC command and then poll DDRY?

After SYNC process, does the data we get is based on our new setting?

Thanks

Y.L

Hi Yuquan,

Take a look at Figure 2 of the the ADS1243 datasheet or Figure 3 of the ADS1243-HT datasheet to see what happens when you change the mux or configuration settings.  The sooner you change the mux following DRDY the lesser the settling error.  The reason is you have partial data from the previous mux connection in the digital filter and have digital filter settling error.  It takes one complete conversion cycle for the digital filter to settle (single cycle settling.)  The ADS1243 does not reset the digital filter when the mux is changed, which differs from some of our other parts, such as the ADS1248.

Using the DSYNC command will reset the digital filter so that there is no digital filter settling error.  What happens is the digital filter goes into reset on the last edge of the SCLK of the DSYNC command but stays in reset until the next rising edge of SCLK.  For example, you could issue the WAKEUP command to bring the ADS1243 out of the digital filter reset hold.  The conversion cycle begins at this point and the next time DRDY transitions from high to low you will have valid data for the selected mux or most recent changes.

Best regards,

Bob B

Sending a wakeup command may need t11 delay after SYNC command. To speed up the process, we would like to send 0xFF by SPI right after SYNC command.

Is this ok?

Thanks

Hi Yuquan,

You must always wait the t11 delay after issuing the DSYNC no matter what command (or NOP data) is sent next.  This delay will be 4 tosc periods (which is the time needed to execute the command and be ready for the next one.)  It is the rising edge of SCLK that starts the conversion cycle and has nothing to do with the command (or data) sent.  In other words, you can send a command or junk data (NOP) it doesn't matter.  If you do issue a command it will execute the command.  The WAKEUP command is a harmless command. 

Best regards,

Bob B

Hello:

 I am experimenting the ODAC ( offset). Bit 7 is the sign bit 0= positive and 1= negative.

The data sheet says our input voltage  Vin(+)-Vin(-) will add this offset voltage.

However, I found the input voltage is actually minus the offset voltage.

Can you check?

Thanks

Y.L

Hi Yuquan,

In past experiments I too have found it to add the inverse of the offset DAC.  I found it easier to think in terms of the desired end result.  If you have a positive offset at the input, the desire is to subtract the value of the offset DAC to get a 0 result.  If you subtract a positive value from a 0 offset you get a negative value. 

Personally I have never found a good enough reason to use the ODAC.  I think a SYSOCAL is a much better approach for adjusting offset.  If attempting to increase the dynamic range it may be helpful, but it also can add error and drift.  Also the additional noise can negate the benefit of increased dynamic range.

Best regards,

Bob B

Hello: We shorted Channel 5 and 7 and use /select channel 5 as negative input, but did not get the right result.

Will the short between channel and 5 cause the problem?

Thanks

Hi Yuquan,

You may have a good understanding on what you are trying to accomplish, but unfortunately I do not.  What result did you get and what are you expecting?  What is connected to channel 7?  Is channel 7 the positive input?

Best regards,

Bob B

Channel 7 is shorted with channel with channel 5 and there is nothing else connected on channel 7.

We are using channel 4 as positive input and channel 5 as negative input.

Our differential in put voltage is known and reference is known, so we know the expected right AD converter  numbers, but we did not get it .

we are taking more than 8 samples at a time.

We have tested channel 0/channel 1 pair and everything is right there.  Now we are testing channel 4/5. And the channel 7 is shorted with channel 5.

Y.L

Hi Yuquan,

That should work, so either your input voltages are outside of the common mode range of the analog inputs or you have a communication error.  Have you verified that the mux register setting is as you wrote it?

Make sure that any input voltage you apply is referred to AGND of the ADS1243.  It should not be a floating input voltage.

Best regards,

Bob B

we got it. Thanks

Hello Bob:

For ADS1243-HT,  we set data format to be Unipolar. Does that mean :

  the analog input is still differential ( Positive channel voltage  - Negative channel voltage)?

To use unipolar, we need to make sure ( Positive channel voltage  - Negative channel voltage +   Offset voltage) to be above ground zero.

Is that right?

Thanks

Y.L

Hi Yuquan,

The ADS1243 measurement is always measured as the difference of the IN+ to the IN- selected inputs.  If IN- is more positive than IN+, then the result will be a negative value in bipolar mode.  This does not mean that IN- can ever be below ground. The analog (AIN) inputs must always be within 0.5V of the supply rails.  This is true no matter the data format selected (both bipolar and unipolar).

The unipolar format allows for measurement in one direction only.  This allows for increasing the dynamic range for measurements where the analog inputs will always have IN+ more positive than IN-.  You assign the IN+ and IN- by choosing the appropriate mux selection.  The actual AIN input must never go more than 0.5V below GND.  If the sensor output goes below GND, then you must use an op amp or instrumentation amp so that the output of the amp is within the correct input range of the ADS1243.

Best regards,

Bob B

In my case , both Vin+ and Vin- are positive., but  Vin+ minus Vin- could be a bit of negative. I want to add Offset so that Vin+ minus Vin- plus Offset will always be positive.

Then I want to use unipolar, will that be Ok?

Thanks

Y.L

Hi Yuquan,

Yes, that should be work fine.

Best regards,

Bob B

Hello Bob:

I would like to do chip selection, then config the digital registers( such as channel selection)  and then take an A/D sample, de-select the chip.

After a while ,  can I select the chip and take A/D sample without redo the digital registers config?

Thanks

Y.L

Hi Yuquan,

Yes, you can operate the ADS1243 in this way.  The registers will retain the values written unless you overwrite the registers with new data, or if the device is reset.

Best regards,

Bob B

Hello:

For ADS1243-HT, it says " A/D converter provides up to 24 bits of no
missing code performance", but it also said the effective resolution is 21 bits and it also depends on gain setting.

From firmware design point of view, do I need to figure out the effective bits first and only use the effective bits( if it is , how)

or I can just use the 24 bits?

Thanks

Y.L

Hi Yuquan,

The ADS1243 resolves to the 24-bit level which is the output response.  However due to noise, the effective resolution does decrease from the resolution size.

When writing your code, you can use either method keeping in mind that the LSB size will be determined by the number of bits you are using.  Also, the data from the ADS1243 needs to be adjusted accordingly if you uses fewer than 24 bits.  One method would be to just truncate the desired number of LSBs.  For example, you might have 4 bits of noise.  You could take your data and shift the value to the right by 4 (data>>4) and then use the LSB size of 2^20 instead of 2^24 as it relates to full-scale range.

Best regards,

Bob B

Hello Bob:

I have

range bit setting=1;

unipolar setting

Vref+ =2.5V, Vref-=0V

Gain setting=2

My understanding is that when

differential analog input=0V, then digital output  is zero

.differential analog input=negative,then digital output  is zero

differential analog input=2.5/4=0.625V, then digital output is 0xFFFFFF  ?

max offset voltage setting is: 2.5 /8=0.3125V

Is that right? Correct me if I am wrong

Thanks

Hi Yuquan,

I'm confused as to what you are asking me.  If your reference is 2.5V, then why are you using Range 1?  And why are you trying to offset the result?

It might be better for you to tell me what you are attempting to measure as well as the input range.  Even with the Offset DAC, you cannot measure a voltage below ground as this exceeds the input range.  Also, if you have the Buffer turned on, this exceeds the input range.

Your understanding for the unipolar calculations appear to  be correct.  Using the Offset DAC you can adjust up to 1/2 the input range.  This assumes that you have not exceeded the absolute input range to the ADC.

Best regards,

Bob B

Hello:

Bob, thanks.

 we use range1 , because our power supply is  only about 3.6V and Vref + is 2.5V, Vref- is ground. The data sheet page 18 says we have to use range1.

Adding offset voltage is intended to bring the digital output span centered, when analog log input change from extreme low to extreme high.

Our design is on board,It is not simple to generate the right analog input to check.

It seems I need to generate the analog differential  input voltage and test digital output .

Thanks

Hi Yuquan,

I see now.  I'm sorry in that I should have read through the thread again before posting the last time.  Please keep in mind that the PGA is before the Offset DAC.  When gain is applied the input impedance lowers unless the Buffer is on.  When the Buffer is on, the absolute input range lowers by 1.5V from the supply (and the input signal must be between 0.05V and 2.1V).  Regardless of the Offset DAC setting, you must maintain the required input levels as specified in the datasheet.

I'm not sure I've seen anyone use the device in quite the way you want to use it.  When using the unipolar mode, the analog input is usually a single ended input (referred to ground).  In this way you do not lose a bit as the signal would not go into the negative direction.

Can you be more specific on the actual input voltages to the ADS1243 and the range of change these voltages may take?  In other words, I would like to know the actual voltages at the + input and the - input with respect to ground.  I can then help to determine any issues with the method you are trying to use.

Best regards,

Bob B

ADS1243-HT : SELFCAL command

after reading the data sheet , here is the sequence I come upo with:

 (1)  Turn off buffer

  (2) Range bit  =0

 (3) Disable ODAC: How to? By writing zero to it?

 (4 ) Set PGA=1

(5) Issue SELFCAL

After done,

(6) set PGA needed

(7) Set up range bit,  set up ODC

It that the right sequence?

After self cal, do we need to access the self cal result to adjust ( Subtract) our A/D Data?

Thanks

Y.L

one more question regarding self cal:

After finishing self cal for pressure channel, take pressure data, 

We need to change input channel for temperature measurement. 

Do we need to redo self cal for pressure temperature channel?

Thanks

Y.L

following question on self cal:

Data sheet ADS1243-HT page 10 -11 timing diagram says

after Selfcal command,

(1) I need to wait 4 DRDY period before issuing next command.  (2) The definition of DRDY period/ frequency is on page 35 " Data rate"

Is that true?

I need a software delay for the 4 DRDY period.

Thanks

Y.L

The data sheet  Page 18 also says, once DRDY goes low, it  means self cal is done.

Do you mean after we detect DRDY low, we t still need  to wait  4 DRDY  before issuing next command?

Thanks

Y.L