Hello!! Could you please specify why max value of propagation delay (DRDY falling edge to DOUT MSB valid in SPI Formar or SYNC rising edge to DOUT MSB valid in Frame-Sync ) is given up to 31 ns in datasheet. To my mind it may cause data curruption in the DSP processor. For example in high speed mode we have 37Mhz CLK and SCLK. So period of SCLK about 27 ns. I think that propagation delay should be less then Half of SCLK period... Thus, I need some explaination. May be I don't take some details in account... I'll be happy of any help.
Best regards
