I am debugging a design using multiple daisy chained ADS1278 converters. I am using the TDM SPI mode. The basic design is working, but I am getting some very odd noise patterns on some of the channels. I have removed the input circuitry so all the ADS1278 inputs are shorted (Ain+ to Ain- for each channel, not all channels together) and the weird noise is still there. Most of the time the noise is about 8uV RMS as expected, but sometimes it increases as high as 50uV RMS. The additional noise appears most often on channel 7 of 8, but occasionally shows up on other channels as well. The noise pattern leads me to suspect it is digital in nature, and blowing cool air across the ADS1278 changes the noise, which makes me even more suspicious it is digital in nature, but I'm at a loss as to what to do about it.
The ADC clock and SPI clock are independant signals, but both are generated from the same micro at the same frequency. The SPI clock is only on during the SPI read and it is not the same phase as the ADC clock. I am using the low speed mode with a clock that is configurable for a sample rate of approximately 512-2048Hz The ADS1278 data sheet says the SPI clock should be the same or a power of 2 division of the ADC clock, but I am wondering if there is a phase relationship requirement as well.
I am thinking about driving the ADC and SPI clock from the same source and using the micro's SPI interface in slave mode. I'll need to get a few external chips to try that, but the other concern I have is that the data sheet specifies 1 clock period between the falling edge of DRDY and the first SCLK rising edge and I can't meet that if SCLK and CLK are the same signals.
I would appreciate any ideas on how to fix this problem
