When is the analog input sampled?
i.e. in what time period are the switches in Figure 45 closed?
Thanks for any help you can provide
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Hello Henning,
The sampling switch on this device remains closed whenever the ADC is not converting. A rising edge on the CONVST pin causes the sampling switch to open and the ADC begins converting the (last) analog input value held across the internal sample-and-hold capacitor.
Best Regards,
Harsha Munikoti