ADS131E08 never responds via DOUT

Mr Syrotuck -

Something looks wrong with the signals from the picture that was attached.

• Is CLOCK = SCLK or CLK (master clock)?  Based on your picture, if CLOCK = SCLK, it doesn't look like you are running the SCLK fast enough.  You have to be able to read 216bits per frame (at data rate).
• Once the converter is started, the DRDY signal should be periodic at the selected data rate.

Take a look at Figure 1and Figure 18 in the datasheet for reference.

Thank you for the reply Greg,

Clock is SCLK, The SCLK was running at 62.5 KHz. After finding equation one, i see that it requires ~5.2 MHz (32kSPS, and 16 bit resolution is default) on the SCLK line. I am using an AT90CAN128 whose max SCLK output is only 2MHz, so how do i use the WREG command when i can't reach the SCLK i need. In the end i do want to be able to write to the Config registers to change the data rate to 1 kSPS and 24 bit resolution, requiring only a ~216KHZ SCLK. 

EDIT: Attached is the RREG command (SCLK = 2MHz) for the CONFIG 1. The DRDY goes high when the command is issued, but the datasheet says "... data must be read between two consecutive DRDY signals." i am unsure as to what that means. 

You should be able to issue commands OK at your SCLK.  However, you will need to use the RDATA command instead of RDATAC.  You can read more about this in the datasheet.

This allows the data to latch, but you will probably miss data, and therefore you will have non-contiguous data.