My question is about the DAC121S101QML DAC.
It appears that when a valid serial write is executed, the device will latch and hold
that written value until either a new valid write is received, or the device is powered down.
Is that correct?
Also, can the clock and sync pulses be discontinuous between valid write sequences?
That is, can I turn off SCLK and SYNC_n until I want to do a write?
