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Residual voltage at AVDD, AVSS and DAC7760 Outputs

Other Parts Discussed in Thread: DAC7760

Hi...

We are using DAC7760 with configuration as shown in attached image.

When we are providing external 5V to IC ( without providing +15V to AVDD & -15V to AVSS ), it is observed that there are voltages generated on AVDD, AVSS & All Outputs ( Pin 21 )

AVDD = 1.3 V

AVSS = 0.53 V

All Output Pins = 0.47 V

For testing purpose ( considering, DVDD may put voltage internally on AVDD ), we have test the circuit by keeping DVDD & DVDD-EN pins open / not connected to VCC. 

In this case - 

AVDD = 1.22V

AVSS = 0.22

All IC O/P = 0.075 V (approx )

What could be the reason ?

  • Saurabh,

    I want to make sure I understand this correctly - you have two test cases:

    1. AVDD/AVSS are floating and VCC is applied to your board which provides power to DVDD and weak pull-ups on SCLK and ALARM. DVDD-EN is connected to GND.
    2. AVDD/AVSS are floating and VCC is applied only to the pull-ups on SCLK and ALARM. DVDD-EN is connected to GND and DVDD is floating.
  • Hi Kevin,

    You have understood case 1 correctly.

    In case 2 - DVDD-EN is also open, so that Internal Voltage will get generated at DVDD

    ( This is with reference to Datasheet of DAC 7760  - SBAS528A –JUNE 2013–REVISED DECEMBER 2013 )

    Few points I want to add, which I missed yesterday - 

    There are 4K7 Pull up resistors, connected to following Pins also - 

    Clear ( Pin 6 ), Latch, DIN & SDO

    Thank you.

  • Saurabh,

    There are diode paths that could allow current to conduct from DVDD to AVDD and some of the output stage that would manifest itself on the output pins as well. AVSS diodes are facing the opposite direction, though, and no voltage potential should be able to develop at this pin.

    In case 2 the internal LDO still will not be activated because the AVDD rail is not powering the LDO. In this case the digital core is not powered but ESD diodes on the digital IO pads are conducting and reverse powering the digital block and subsequently leaking into AVDD and the output stage.

    I will need to replicate the tests to see if I can observe voltage potentials developed on the AVSS line.