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ADS1248 system clock and noise

Chris Forte
Intellectual 310 points
Other Parts Discussed in Thread: ADS1248

Hi Joseph,

What are the trade-offs regarding the system clock? For better noise performance should I use an external clock at 1Mhz?

Thank you,

Chris

  • 0
    TI__Guru* 92655 points

    Chris,


    Generically, I don't think there are any trade offs with the system clock and noise. The original noise measurements for the ADS1248 reported in the datasheet are made with the typical system clock of at 4.096 MHz near the upper limit of 4.5 MHz, and the noise won't get better at lower frequencies.

    However, the system noise you see may be larger because of external noise and the response of the digital filter. At low data rates using a 4.096 MHz clock, the digital filter are tuned to reject 50 and 60 Hz noise (look at the figures 54-58 in the datasheet). At different clock frequencies, these notch frequencies may not cover the power lines. Depending on the environment, this power line noise can be pretty large.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Intellectual 310 points

    Joseph,

    One more question please. The tsccs parameter on page 10 is referenced to the tosc . I would think it should be related to tsclk. Can you confirm that I should use the system clk when implementing this hold time for the serial clock?

  • 0 in reply to Chris Forte
    TI__Guru* 92655 points

    Chris,


    The SCLK low to /CS high hold time is referenced to the oscillator clock.

    With the exception of clocking out the data, everything internal to the device happens based on the oscillator clock. After the last clock of the read, SCLK must be held for another 7 oscillator periods. While you may still get the output data you want, the ADS1248 still tracks SCLKs for input data and the number of bytes that is read in.


    Joseph Wu