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ADS1672 offset error by AVDD

toshi-e2e
Genius 4705 points
Other Parts Discussed in Thread: ADS1672

Hi, all!

My customer has questions about ADS1672 offset error.

When AVDD was changed from 4.75 V to 5.25 V , the offset was varied by about 250 uV.

The test condition is as follows;

 - Test circuit is almost the same as Figure 39. Basic Analog Signal Connection of Page 26. 
 - Low-Latency, Fast-Response
 - Sampling frequency: 125 kHz
 - DVDD = 3.3 V
 - fck = 20 MHz
 - Vref =+3 V
 - Rbias = 7.5 kΩ
 - Input level: AINP = AINN = 2.5 V

  1. Meaning of the PSSR is a variation of Full scale  with respect to the change in the power supply voltage.
     Is it right?
     Is PSSR is related with OFFSET error? 

  2. How much is change of OFFSET to change of AVDD?
　　
  3. Is the 250uV offset change the performance of ADS1672? 　

Regards,
Toshi
　　  　


 

  • 0
    TI__Mastermind 23235 points

    PSRR is calculated using the change in the power supply in relation to the change in the output.

    Based on the variation that you are seeing, it seems like 250uV is on the higher side.  From the datasheet, the typical value is 92dB, so the offset should be a little smaller that you are measuring.

    Are they using the EVM? Or is it there own configuration?
    Are the inputs shorted? Or are they just both tied to 2.5V (as indicated above)?

  • 0 in reply to Greg Hupp
    Genius 4705 points

    Greg-san,
    Thanks for your reply.

    They are using their own configuration.
    The results are almost same when they measured the change of offset vs the change of AVDD on two boards.
    The inputs are shorted and are tied to 2.5V.

    Is there any solution for decreasing the change of offset?

    Best regards,
    Toshi

     

  • 0 in reply to toshi-e2e
    TI__Mastermind 23235 points

    Hi Toshi -

    It is a little hard to provide recommendations without knowing more about how the customer circuit is designed.

    General ideas:

    They should make sure the decoupling capacitance for the chip is close to the device and of adequate value (see EVM schematic).  Depending on the power supply source, the supply could be contributing more ripple/noise at the higher end of the voltage range.

    They should make sure the ground connection is solid.

    Make sure they are buffering the voltage reference.  Without buffering, the noise could be increased.

  • 0 in reply to Greg Hupp
    Genius 4705 points

    Hi Greg-san,

    Thanks for your advice.

    Customer would like to know the change in offset..
    May I ask you to measure the change in offset when AVDD is changed from 4.75 V to 5.25 V ?

    Now, I informed your advice to my customer and asked them to check their circuit and PCB pattern by referring EMV user's guide.

    Regards,
    Toshi