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ADS1178 No _DRDY (Active Low Data Ready) response

Other Parts Discussed in Thread: ADS1178, ADS1278

Greetings!  I am working on a project utilizing the ADS1178 and am testing the chip at a component level right now.  I am having a bit of an issue generating a response from the chip at all.  I have attached the chip to a 64 pin breakout board and am attempting to interface it with the following parameters

Clock divider =  0
Format = 001  (SPI TDM fixed)
Mode = 1 (Low Power)
Clock = 5.32 MHz

SClock = 665 KHz (1/8 ratio to meet timing standards as per datasheet)

My hardware configuration is based on the example schematic from the datasheet, save for the difference in format and timing. I have a single ended accelerometer (ADXL326) attached to the input of channel 1, but that is of no consequence because as of right now the chip does not generate a _DRDY pulse, nor does it respond to the SPI SCLK (I have mointored both with an O-scope and have seen no response regardless of duration of the SYNC pulse or SPI prompt). My initial thought is that maybe the core is not getting enough power (the DVDD pin). I am interfacing with an mbed uController (LPC1768) during the prototype stage if that is of any significance?

  • Hi Matthew,

    I apologize for missing this post. Do you still need help with this?

    What supply voltages are used for AVDD, DVDD, and IOVDD and are they brought up in the correct sequence? If so, /DRDY should drop from high to low after 218 master clock periods + 129 data rate periods.

    So in your case:

    CLK = 5.32 MHz CLK

    Low-Power Mode, CLKDIV = 0 -> Data Rate = 5.32 MHz / 256 = 20.78 kHz

    /DRDY will fall after (218 / 5.32 MHz) + (129 / 20.78 kHz)

    Ensure that that /SYNC is also held high in order for the modulator to begin converting. If /SYNC is held low, /DRDY will remain high.

    Best Regards,

  • A little confused, I am referencing the datasheet and under low power mode, Clock divider 0,  the Fdata value reads 512 (Table 4).  Where is the 256 value derived from?

  • Additionally I was able to generate a _DRDY recurring pulse.  However this was only attainable after forcing the _SYNC value high for close to 60ms (I switched the CLKDIV value to 1 at some point due to my project requirement of needing to eventually daisy chain 36 channels).  My sample rate for my project is 100 Hz, so I would like to be able to throw _SYNC low every 10ms and be able to collect the 36 channels of data before the next _SYNC pulse.

  • Sorry to keep stretching this thread, I am aware that a segmented DOUT scheme can be used to increase my number of channels.  This may be the course of action I take as I proceed.  I had originally wanted to keep the input limited to 1 SPI line but I do have an additional SPI line available.

  • Hi Matthew,

    Let me try to catch up here... :)

    Good catch on the "fCLK / 256." That ratio is only valid for the ADS1278. In ADS1178 Low-Power Mode (CLKDIV = 0), fCLK / fDATA = 512.

    With that, (218 / 5.32 MHz) + (129 / 10.391 kHz) = 61.69 ms, which is the expected time it should take from /SYNC high to /DRDY falling low.

    Once the device is up and running, you can pulse the /SYNC pin low to stop conversions and reset the digital filter. When /SYNC is brought low, /DRDY will be held high. Upon bringing /SYNC high again, you will only have to wait 129 conversions (129 / 10.391 kHz = 12.4 ms) before data is valid again, indicated by /DRDY falling back low.

    The /SYNC pin is most commonly used to synchronize multiple devices and control when the digital filter resets. The intention is not to control the data rate manually. The architecture of delta-sigma ADCs is optimized for continuous time data collection; it is not intended to be used to take "snapshots" of data like a SAR ADC.

    If you change CLKDIV to 1 (which earlier you mentioned considering), you can produce a Data Rate of 100 Hz with a 256 kHz master clock. Will that work for you?

    Let me know if this makes sense or if you have more questions.

    Best Regards,

  • This absolutely answered my question, and thank you for pointing out the Delta Sigma function, I thought I had wrapped my head around this stuff, but clearly I hadn't.  My goal IS to grab simultaneously sampled "snapshots" of data.  I was under the impression that that was what this ADC was designed for as the Title of the datasheet read "Quad Octal, Simultaneous Sampling".  I will look more towards an SAR ADC that will meet my specifications (I am trying to sample from 36 sensors simultaneously).  Thank you for your patience, I am a college Computer Engineering intern and am still feeling my way through a lot of this.  And if you have any suggestions for a good SAR ADC with daisey chaining capabilities available through TI please let me know :-)   

  • Glad I could help!

    I would suggest perusing the Precision SAR ADC portfolio here. The device you choose will depend on your application, required resolution, bandwidth, etc. You can start a new post under the same forum to get advice from our SAR counterparts.

    Best Regards,