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ADS1274 CLK vs. SCLK

Ole Nielsen
Prodigy 10 points
Other Parts Discussed in Thread: ADS1274

For the sake of flexibility in a design with the ADS1274 we'd like to run the sampling rate (governed by the CLK) and the serial data rate (governed by the SCLK) independently, only restricted by the limits that ensure correct serial data transfer from the ADS1274.

The ADS1274 data sheet states that "For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc.". However, there's no indication of what actually happens if the SCLK frequency does not equal the CLK frequency divided by an even integer ratio.

Does TI have any data or measurements that quantify the performance loss when running the ADS1274 at other SCLK frequencies so that we're able to make a proper performance budget?

  • 0
    TI__Guru 57336 points

    Hello Ole, 

    Thanks for your question.

    I understand that this statement is not entirely clear. You certainly can run the SCLK and CLK at speeds that are not in a 1 / 2n ratio. However, when the SCLK and CLK are not in this ratio, their periods will be out of phase, causing the noise floor of ADC to increase slightly. This increase in noise will still remain within the maximum specs listed in the device datasheet, so that is what I would use in your performance budget calculations. For the lowest noise performance, we suggest keeping SCLK and CLK are kept phase with one another.

    Best Regards,