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ADS1147 Problem communicating via SPI

JEFF CLAWSON
Prodigy 50 points
Other Parts Discussed in Thread: ADS1147

Hello,

I’m having problems communicating to the ADS1147 via SPI.  I have the below circuit on a PCB.  The circuit also includes a SPI LCD display which is working fine.

 

The SPI is running at 50Khz, MSB first, low idle clock.   Reset is high.  What are the other timing requirements. 

  • 0
    TI__Guru* 92655 points

    Jeff,


    What sort of problems are you having? All the timing information you need should be on pages 12 and 13 on the datasheet.

    If you describe what data you are getting out, it would help with debugging this problem.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 50 points

    Joseph,

    I'm not able to get any data.  All reads are 0x00.  The writes are also not working.  Part of my code sets the sample rate to 10SPS, (the default is 5SPS).  I can see the drdy signal pulsing at 200ms rate...5SPS derfault value. 

    Jeff

  • 0 in reply to JEFF CLAWSON
    TI__Guru* 92655 points

    Jeff,


    It's good that you can see the DRDY pulses. That would be one of the first things to check. This way you know the device is converting, even if you can't get to the data yet.

    I would first verify a few things. First make sure you're using the correct flavor of SPI. SCLK dwells low, Signals are clocked in and out on the falling edges of SCLK. It looks from the scope photo that you've got that correct.

    I'd also try to show the DOUT and /CS lines on a scope photo if you have an extra two channels on the scope. Make sure that the /CS line is going low each time you want to clock data in or out of the device. /CS should be continuous until you are done with the communication transaction (i.e. the /CS stays low through communication, not just for each transmitted byte). Clocking in data, you should be able to do this when you choose. For clocking out data, you want to do this after a /DRDY pulse goes low.

    If you are able to show all four channels on the scope, you want to make sure that it looks like Figure 1 in the datasheet on page 12, showing the serial interface timing. You can throw up the picture of the result after you're done. As a side note, I would say that SDATAC does not stop the device from converting, it simply stops the device from updating the output register with new data (in case you were waiting for the /DRDY pulses to stop).

    If you can, start by changing the data output rate, if you can see the /DRDY pulses change frequency, you'll know that the input data was received by the device.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 50 points

    7041.Reg SYS0 register write.docx

    Here's the SYS0 Register write command .  The command did not change the sample rate to 10SPS :(

  • 0 in reply to JEFF CLAWSON
    TI__Guru** 112765 points

    Hi Jeff,

    As Joseph stated in his last post, CS must stay low throughout the entire communication transaction.  You are pulsing CS at each 8 clocks which in turn cancels the data sent previously by resetting the SPI communications. 

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 50 points

    Thanks Joseph and Bob, that fixed my problem. 

    I don't think the timing diagram on sheet 12 is clear about keeping the CS low for all bytes of a single command.   

    Just happy that it's working now!

  • 0 in reply to JEFF CLAWSON
    TI__Guru** 112765 points

    Hi Jeff,

    Unfortunately it is sometimes a little difficult to show all the timing based on one diagram.  The reason being is there are single byte commands and multi-byte communications.  For reference the CS is discussed on page 30 of the ADS1147 datasheeet where it states that CS must stay low throughout the entire communications transaction.  It is also demonstrated in figures 51 and 52 near the end of the datasheet.

    Best regards,

    Bob B