• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 45 subscribers
  • Views 731 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1120 / SPI interface

K.Yaita
Guru 29690 points
Other Parts Discussed in Thread: ADS1120
Hi Team,
 
I'd like to ask about SPI I/F of ADS1120.
In datasheet page.6, there is following description.
------------------------------------------------------------------------
(2) If a complete command is not sent within 13955 · tMOD (normal mode, duty-cycle mode) or 27910 · tMOD (turbo mode), the serial interface resets and the next SCLK pulse starts a new communication cycle.
tMOD = 1 / fMOD. Modulator frequency (fMOD) is 256 kHz in normal and duty-cycle mode and 512 kHz in turbo mode, when using the internal oscillator or an external 4.096-MHz clock.
------------------------------------------------------------------------
I believe the duration of "complete command" is from first  SCLK falling edge to last SCLK falling edge for the command.
Is my understanding correct?
 
Best Regards,
Yaita / Japan disty
  • 0
    TI__Guru** 112895 points

    Hi Yaita-san,

    At the beginning of the command sequence the internal communication clock will begin at the rising edge of SCLK and must be finished within the time interval given in the datasheet.  So the interval begins at the rising edge and ends the sequence on the falling edge.  In other words, the communication begins on the first rising edge of SCLK and completes at the last falling edge of SCLK that completes the command.  This complete communication must be within the timing parameter of 13955*tmod in normal mode or 27910*tmod in turbo mode.  The actual length in time will depend on the source/speed of the clock source used to establish the modulator clock.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    TI__Guru** 112895 points

    Hi Yaita-san,

    My colleague suggested I make one further clarification regarding the timeout.  Some commands are single-byte and some are multi-byte.  The timeout period includes the whole command sequence and not just the command byte itself.  For example, on a read/write register, which are multi-byte sequences, the entire command sequence must be completed before the end of the timeout period.  So the communication of the falling edge of the last byte of register contents (as specified in the command byte) must be completed before the end of the timeout period or the SPI will be reset.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Guru 29690 points
    Hi Bob-san,
     
    Thank you for your detail explanation.
     
    Best Regards,
    Yaita