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ADS8568 daisy chain mode problems

hakan aydin
Intellectual 470 points
Other Parts Discussed in Thread: ADS8568

Hello,

We're having a problem with Two ADS8568 converters in daisy chain configuration. The converters are driven by an FPGA. We're in software mode. We use only a single data line to communicate out of the four available. All channels of all ADCs are tied to the same CONVST.

There are two major problems:
- One of the converters always returns all zeros (this is the first ADC in the chain). This ADC is working with 2.5Vref (can confirm from the pins), in 4XVREF mode
- The other converter (last one in the chain), returns some data, but the data is not correct. This converter also has an incorrect VREF (somewhere around < 100mV range) when we look at its pin.

When data conversion starts and the ADCs start sending data, the first 8 results that come out are incorrect (we presume this is the last ADC in the chain), followed by the next 8 results which are all zeros.

We previously used the same ADC on another board successfully, in single configuration (no daisy chaining). We're using the same Verilog code base to drive this board as well.

Any ideas how to go about debugging this problem?

  • 0
    TI__Guru**** 168605 points

    Hi Hakan,

    Can we start with a schematic?  Can you send me the detail around the ADS8568 devices?

  • 0 in reply to Tom Hendrick
    Prodigy 110 points

    Hi, is there any update on this problem? I'm having about the same thing happen to me... 

    Thanks

  • 0 in reply to Lathom Louco
    TI__Guru**** 168605 points
    Hi Lathom,

    We never heard back from Hakan on this issue so I suspect it was worked out. Can you provide some additional detail, like a schematic and/or timing wave-forms?
  • 0 in reply to Tom Hendrick
    Prodigy 110 points

    Hi Tom, sure thing. Unfortunately the forum won't let me post a picture (screen shot)...  so attached is a word file of it, please let me know if I'm missing anything

    titan ADC daisy chain.docx

  • 0 in reply to Tom Hendrick
    Intellectual 470 points

    Hello,


    We sorted this issue out with TI support. I thought we had agreed that our contact was going to update this thread but I guess it never happened. Maybe a miscommunication...

    We had several problems:

    - First, we thought that the SDI's and SDO's are chained, in all modes. So we connected the SDO of the first ADC to to the SDI of the second ADC.
    - We also thought that the path for configuration data is the same for the path for output data, in all modes. However, this appears to be only true for single ADC mode.
    - We further thought that in daisy chained mode, we could get away with a single serial line for data output (just like single ADC mode), which also doesn't appear to be the case.

    So for the respin of the board, we made sure that:

    - In a daisy chain configuration, the SDI input of all ADCs should be driven simultaneously. Or, alternatively, they can be driven from two different FPGA lines to the same effect.

    - All 4 SDO outputs of the ADCs MUST be tied to the DCIN inputs of the next ADC. The last ADC should send all 4 lines to the FPGA.

    Hope this helps

  • 0 in reply to hakan aydin
    Prodigy 110 points

    Hakan,

    Thanks a lot for the comments. Yes it seems as though that all 4 data lines must be connected in between the daisy chained devices. I'm having trouble configuring the second (of 2) device however. You still had SPI_DI into both devices? I have this now and am not able to properly configure both devices (I think).

    Tom,

    Can you comment please?

    Thanks! 

  • 0 in reply to Lathom Louco
    Prodigy 110 points
    Also, do we only need to watch the data ready on the second device?
  • 0 in reply to Lathom Louco
    TI__Guru**** 168605 points

    Hi Lathom,

    If both devices are to be configured the same way, you can connect the two SDI and /CS pins together and send the configuration detail to both simultaneously.  If they will have different configurations, the two devices can share the SDI line, but they would have to have independent chip selects.  In your schematic, it looks like all CONVSTs are tied together so there is no need to monitor BUSY from device 1.

  • 0 in reply to Tom Hendrick
    Prodigy 110 points
    Thanks Tom,
    And we should still be able to read data out in serial correct? (even though it's being passed in parallel)
  • 0 in reply to Lathom Louco
    TI__Guru**** 168605 points
    Hi Lathom,

    You need to look at all SDO's - the last device in the chain does not know how many devices are 'downstream' so there is really no way to serialize all the data through a single SDO at the end of the chain.
  • 0 in reply to Tom Hendrick
    Prodigy 110 points
    Hi Tom,

    Thanks for the info. I think I understand but am confused on what to do with it. How does that connect to a single SPI? Or does this mean, if you daisy chain these chips, you can no longer do that...

    Thanks,
    Lathom