I have 2 synthesizers. One generates a signal that will go to 6 different circuits, generating signals that I'm intending to sample with the ADS1278. The second synth will generate the clock for the A/D Converter.. I intend to turn on boths synths simultaneously (both coming out of RESET, at this point SYNC is LOW). I intend to collect about 52000 samples/sec working in low power mode using a CLK of about 13.2Mhz. for about 3 seconds (CLKDIV =0). Then everything gets reset and the process starts all over again Only 6 channels will be running in the A/D. I would like to collect the data thru a single DOUT. SPI mode is what I think I would like to use as a response from DRDY ( a "you have data" interrupt) . I intend to pulse the data out of the A/D with a 10 MHz clock. I intend to use dynamic position data. A signal in my system turns on the 2 synthesizers always at the same time and in the same way. I use an FPGA to generate a signal synchronized with CLK to drive SYNC high to start the A/D conversion, about 200ms after starting the synth's.129 data points converted later, I expect to start receiving data ... The questions I have are: 1. My 10 Mhz clock is completely asynchronous from the A/D clock ... should I expect any problems? When I turn SYNC low, it seems that DOUT1 goes low and 129 conversions will get lost ... is this correct? Finally Table 13 says that tSYN should be at least one CLK period. The picture above (Synchronization Timing) shows tSYN smaller than a CLK period ...