• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 47 subscribers
  • Views 850 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS131E08 Fault_stat and oscillator

Nadja Peters
Prodigy 50 points
Other Parts Discussed in Thread: ADS131E08, ADS131E06, ADS131E08S

Dear all,

I have two daisy chained ADS131E08 converters. Both are powered single supply, AVSS is GND and AVDD is 3.3 volts. My reference voltage is 3 Volts, nref is also connected to GND. Now I have some questions:

1) I am triggering out data in SDATAC mode. When clocking out the data after drdy was triggered, I get the following result: The fault stop n bits are all set to 1. I assume that there must be an error somewhere. Where should I start looking for it?

2) I am using the clk_en bit to output the clock of the first adc and then I use it as input for the second adc (page 36 datasheet). Is this a correct way to operate the device?

Thank you!  

  • 0
    Prodigy 50 points

    Another question:

    3) Is it possible to put an ADS131E08 and an ADS131E06, two different parts of the same family, in daisy-chain mode?

  • 0 in reply to Nadja Peters
    TI__Mastermind 43915 points

    Hi Nadja,

    You are able to chain an E06 and E08. Two ways you can do it.

    1. If you cascade the E08 followed by the E06, it will be more efficient to get the data out. After the E08 data, the E06 will seemlessly follow.

    2. If you cascade the E06 followed by the E08, you will need to send more clocks. You will shift out 6 channels from the E06 followed by 2x24 bits of all zeroes (for removed channels 7 and 8 on E06) then the shifted out data from the chained E08.

    My recommendation is to configure as #1 if possible.

    Regards,

    Tony 

  • 0 in reply to Tony Calabria
    Prodigy 50 points

    Thank you, Tony, for the advice. This may ease some further development of my current project. I still have the other two questions where I did not find satisfying answers in the data sheet:

    1) I am triggering out data in SDATAC mode. When clocking out the data after drdy was triggered, I get the following result: The fault stop n bits are all set to 1. I assume that there must be an error somewhere. Where should I start looking for it? Most of my negative signals are tight to ground.

    2) I am using the clk_en bit to output the clock of the first adc and then I use it as input for the second adc (page 36 datasheet). Is this a correct way to operate the device? It seems so from the datasheet but I am not sure.

  • 0 in reply to Nadja Peters
    TI__Mastermind 43915 points

    Hi Nadja,

    Sorry for the delay. I will do my best to answer your questions.

    1. Not sure I understand question #1. If you are using single supply configuration, tying half the inputs to GND, you will be triggering the internal comparitor triggering the fault bits. Could you explain your supply configuration and what voltage you have on the individual inputs when the fault bits are triggered?

    2. Depends on what is good enough. I can tell you that the best performance you can achieve from the ADC is if you use an external clock. The internal oscillator does have some noise associated with it which would degrade the DC performance.

    Aside from that, if you decide to use a clock from device 1 to feed device 2, you need to keep in mind the pad delays and trace routing delays which could bring the two ADCs slightly out of sync. If you use an external clock and tree it off to feed two ADCs, you may have better luck synchronizing.  

    Thanks,

    Tony

  • 0 in reply to Tony Calabria
    Prodigy 50 points

    Hi Tony,

    thank you for the answer. So for my next design, I will definetely put an external oscillator. The note in the datasheet (page 36) is irritating.

    My supply configuration is as follows:  I have 3.3 V analog supply and 3 V digital supply. Both grounds are connected via a gnd layer. I have also a external reference 3 V reference. I have also daisychained to ADS131E08s. I have all n-pins connected to ground, also reference voltage. Test pins are also connected to gnd. p-channels of input 2, 4, 6, 8, and 2 of the second ADC are connected to analog VCC, which is 3.3 V. The other pins are connected to values close to gnd. I have the fault bits set to one for all the pins.

    For setting up the device, I send the command to output external clock. No more commands.

    Thank you! 

  • 0 in reply to Nadja Peters
    Prodigy 50 points
    So what I still do not understand is why the fault bits are triggered.
  • 0 in reply to Tony Calabria
    TI__Mastermind 23235 points
    Hello Nadja -
    In response to your question regarding the fault flags:
    Since you are inputting a full-scale signal, then this is correct operation since the comparator by default are based off of 95% and 5% of the full-scale signal.