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ADS1278 Octal, 144kHz, Simultaneous Sampling 24-Bit Delta Sigma ADC, Sampling Freeze Problem

Rovshan Zaharaev1
Prodigy 20 points
Other Parts Discussed in Thread: ADS1278

Hi,

I use ADS1278 Octal, 144kHz, Simultaneous Sampling 24-Bit Delta Sigma ADC.

I have problem with DRDY indication that freeze sometimes, for 128clocks of 1/fdata.

Seem that ADC have configuration change althought no one of digital control signals was changed.

ADC works in SPI interface with high speed mode. Each sample takes 256 clocks.

ADC1278 connected to SPARTAN6 FPGA and sample clock is about 13MHz (50*1024*256 =13.1072MHz).

I put trigger on DRDY signal and according to injected clock this signal is activates low every 19.usec, but sometimes with random time DRDY remaining high for 2.5msec, This time is exactly 128clocks of 1/fdata that can be from any configuration changes.

I sampled every conrol signals to DRDY freeze time occurance but no one of them had changed before and after. 

I also check digital volatages at this time , also there was no any changes that can reset ADC.

Sync pulse inserted once time and remain high for all time. This phonomenon occurs after all configuration and repeat after some seconds or some minutes.

Seems that external noise can trigger DRDY freeze. If I put my card to noises place near system power supply this problem occurense appearance increased.

Any suggestions?

Thanks

Rovshan

  • 0
    TI__Guru 57296 points

    Hello Rovshan,

    Welcome to our forum.

    As you mentioned, /DRDY should only be held high when

    a.) there is a MODE[2:0] change, or

    b.) the SYNC pin is pulsed.

    Since you are doing neither of those things at the time that /DRDY “freezes,” there must be something inadvertently toggling or shifting on the digital I/O pins.

    Triggering the scope on each of the MODE pins would have been my first suggestion. Take a close look at the channel /PWDN pins as well as the FORMAT pins too. I’m not sure whether changing these pins would hold /DRDY high or not, but the same settling time specs would still apply for the data to be considered valid.

    Also, I would verify that nothing is spiking on your ground and power supply pins.

    Keep me posted on your findings and I will let you know if I think of anything else.

    Best Regards,

  • 0 in reply to Ryan Andrews
    TI__Guru 57296 points

    Hi Rovshan,

    We looked at the digital design once more and confirmed that the only things which cause a mode change reset (after which /DRDY is held high for max 129 conversions) are the SYNC pin, the MODE pins, and the CLKDIV pin.

    I would like to refer back to your original post for more clarification. When you said "Seem that ADC have configuration change althought no one of digital control signals was changed,” did you confirm that the MODE and CLKDIV pins remained the same? Did the ADC output data rate change to indicate that the mode was different?

    Finally, you mentioned that this problem increases when the system is placed closer to a noise source. Are the digital control pins pulled high/low to the digital supplies, or are they controlled through a GPIO on your MCU?

    Best Regards,

  • 0 in reply to Ryan Andrews
    Prodigy 20 points

    Hi Ryan,

    Thanks a lot for quick response,

    All digital control signal (include CLKDIV and mode[1:0]) are connected to Xilinx Spartan6 FPGA. All control lines configured at reset and doesn't have any changes later.

    I sampled all ADC conrol signals in scope , but no one of them changed before and after DRDY freeze.

    I have added pull ups and pull down to this signals in Spartan6, but this change still  didn't solve DRDY freeze problem.

    Regarding to your question about ADC sampling rate: Sample clock is fixed frequency.

    Thanks,

    Rovshan