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ADC128S102 Frequency of Operation

Keith Newlander
Prodigy 50 points
Other Parts Discussed in Thread: ADC128S102, ADC128S052

Looking at the ADC128S102QML part, what is meant by note (2) in the datasheet on page 6?

I am operating this part at 6MHz at the moment and want to know if the values in the datasheet are valid for this frequency of operation?

Mainly for the DOUT access and hold times. 

As another question, is there a minimum Access Time for DOUT or shall 0ns be assumed?

Thanks

  • 0
    TI__Prodigy 725 points
    Keith,
    sorry, I can not find a Note 2 on page 6. Maybe you are looking to version of the data sheet which is different from the on eon our web site?
    The ADC128S102QML is pecified with a serial clock (SCLK) which is also the ocnversion clock, from 0.8 to 16 MHz. So if you operate the part with 6MHz, you are all fine.
    Andreas
  • 0
    TI__Prodigy 725 points
    and I did not see your second question. The DOUT access time is specified on pg 7, as 27ns (max).
  • 0 in reply to Andreas Kraemer
    Prodigy 50 points

    Thanks Andreas, you are exactly right about the datasheet.  I must have had an older version because while it did have fsclk_min as 0.8MHz it had the performance specification over the range 8MHz to 16MHz (probably a typo).  Also, note (2) is now present looking at the version directly off the TI website.

    As for the DOUT access time, is there a minimum?   Currently I am just using the range 0ns to 27ns as the DOUT access time but would like to tighten that range if I can since I assume it's closer to 17ns to 27ns (typical to max) and not likely to fall below some minimum access time.

    Thanks

  • 0 in reply to Keith Newlander
    TI__Prodigy 725 points

    Keith,

    the access time tDACC is 27ns max, this is the time you have to wait, to be sure that the DOUT signal has valid state. I would suggest, that you read (synchronise) DOUT with the rising edge of SCLK.

    Also see timing diagram pg 8 of the data sheet.

    Andreas

  • 0 in reply to Andreas Kraemer
    Prodigy 50 points

    Andreas,

    Thanks again for your input. I figured out why I kept seeing 8MHz as a performance minimum and that is from the current Jan 2015 Revision of the ADC128S102. See page 7 under AC ELECTRICAL CHARACTERISTICS it lists FsclkMIN as 8MHz with TYP being 0.8MHZ. I am not sure why TYP is 0.8 and MIN 8MHz, this seems to contradict. The ADC128S102QML datasheet seems to fix this issue, having 0.8MHz as minimum.

    About the DOUT Access Time Minimum, I'll explain why I think the minimum time would be useful to know. The DOUT minimum determines how fast the next edge could occur. Basically setting the upper limit on delay when sampling DOUT, while the DOUT Access Time Maxium sets the lower limit assuming not path delays. Now, my system has a couple of ADCs sharing the same ADC controller that wants to sample at the same point but operate with different path delays. To find the best sampling point, I want to be in between the min and max points. Using the DOUT access time minimum as 0ns gives a wide range, which I can use but would prefer to define that more closer to actual if TI had a minimum they could provide.

    Thanks,
    Keith

  • 0 in reply to Keith Newlander
    TI__Prodigy 725 points

    Keith,

    the 27ns is the time you are looking for. Sometimes, reading EC tables you need to think a bit arround corners.

    What I understand you are looking for is the minimum time you need to wait until the data bit is valid. Correct?

    This minimum time has a maximum of 27ns.

    What the data sheets says: "a typical part (most parts) will have the data bit valid after 17ns, but there will be some where the data bit takes longer, for a few it might be up to 27ns. But you can be sure, there is no part which takes more than 27ns for this"

    In other words, do not try to read the data bit before 27ns after the falling edge of the clock, on some parts the data bit might not be valid before this time.

    Does that make sense?
    Andreas

  • 0 in reply to Andreas Kraemer
    Prodigy 50 points

    Andreas,

    I am asking about the maximum time I can wait.  To know that you need to know the minimum (or assume 0ns worst case).  You are correct, the maximum 27ns defines the minimum waiting time to know the bit is valid.  However, to know the maximum waiting time the minimum delay would need to be known.  Since the maximum waiting time would be DOUT ACCESS TIME MINIMUM + SCLK PERIOD.  Of course, the datasheet timing assumes sampling on rising edges is best case, that only applies if the path delays are not large.  Once the trace path delays or FPGA internal delays become large enough, it's better to sample between the minimum and maximum delays, which may not be the rising edge (as is the case in my design).  What I am trying to say, is knowing a true lower bound would help constrain the range of optimal sample times (by increasing the maximum delay before a new bit transition could occur).  So, at this time, I am using 0ns as a minimum but would prefer to use something more well defined (since I know 0ns isn't truly possible, there must be a minimum it just isn't stated in the datasheet).  Basically, I am asking about the opposite side of the transition then you are discussing.

    Did you by chance look at the ADC128S102 datasheet vs. the ADC128S102QML?  I am using the QML part, which seems to have the correct tables but the non-QML datasheet indicates 8MHz as lower bound with 0.8MHz typical.  I think that's a mistake in the datasheet.

    Thanks,

    Keith

  • 0 in reply to Keith Newlander
    TI__Prodigy 725 points
    Keith,
    sorry that it takes so many posts, for me to understand your question. Maybe I get it this time.
    You can read your data bit in a time interval from falling edge of SCLK + 27ns until next falling edge - 11ns (TDHLD).
    About your second question.
    The QML part is specified (guaranteed) to work from 50ksps up to 1MSPS, this translates to SCLK from 0.8MHz to 16MHz.
    The commercial part, we have 3 different speed grades. The ADC128S102 (without QML) is specified to work from 500ksps up to 1MSPS, SCLK from 8MHz to 16MHz. If you want to use the commercial version with a SCLK of 6MHz, you would need to use the ADC128S052, which is specified for 200 to 500ksps.
    Important to note for you, the QML and the commercial parts have similar part numbers, but they are different parts. So for your design, using the QML part, you need to use the QML data sheet.
    Hope this explains?Andreas
  • 0 in reply to Andreas Kraemer
    Prodigy 50 points
    Andreas,

    I think that clears up most everything. One lat remaining bit on the ADC128S102 datasheet though, is it lists a TYP value of 0.8MHz. Should that be there if the part is specified over 8MHz to 16MHz? Seems a bit confusing.