Hi,
On pg. 48 of ADS1120 ug there is a block of pseudo code (attached below):
There are 3(?) types of delay in it:
- Power up delay (marked orange) - 50 us after power up per section "Reset and Power up" on page 31.
- CS going low/high (yellow) - 50/25 ns respecitvely (t_CSSC/t_SCCS per figure 1 on page 6).
- Some unknown delay (green) between SPI commands
I found a reference on this post saying "A delay time of 50us should cover most cases.."
Since in my application the ADC is accessed from within DRDY interrupt, 50 us delays are very long (unless it is mandatory).
Can someone on TI side look into it, confirm the above orange/yellow timing requirements and most important guide what should be the ACTUAL delays requested, especially between SPI commands (the "green" ones).
Many thanks in advance.
