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ADS1232 - No data clocked out

Other Parts Discussed in Thread: ADS1232

Hello,

I'm currently testing ADS1232 in a load cell measuring system and I'm experiencing some difficulties while trying to clock out data from it.

In fact, no data is clocked out at all.  However, /DRDY is brought low on every conversion (at either speed 10 & 80 Samples/sec).

I'm using 5V DVDD/AVDD

Any help would be greatly appreciated

Here's a screenshots from my logic analyzer when the system is powered up

On every _DRDY/DOUT falling edge, I'm sending 24 SCLK pulses (tried 25 & 26...  didn't change anything).  No data is clocked out

Here's the schematic 

  • Hi Emmanual,

    Welcome to the forum! This seems very unusual.  Can you give me the voltages on the pins for each control pin of the ADS1232?  What exact value are you using for the EMI filters, especially on the SPI lines DOUT/DRDY and SCLK?

    It almost appears as if the ADS1232 is not seeing SCLK at all.  Are you probing near the micro?  If so, try probing at the ADS1232 SCLK pin to make sure that the device is seeing SCLK.  Make sure that you have good solder connections and that the EMI filter cap is not causing an issue.

    Best regards,

    Bob B

  • Thanks for your prompt reply Bob,

    Voltages:
    A0: 0V
    TEMP: 0V (or 4.96V Software selectable)
    GAIN0, GAIN1: 0V (or 4.96V dip-sw selectable)
    SPEED 0V (or 4.96V dip-sw selectable)

    I'm using 100pF filters for all digital signals. (Schematic is mostly based on ref design)

    I'm currently probing directly on ADS1232 pins. I'll check signals rise/fall time to make sure they are within specs.
    Then, I'll jump EMI filters to see if there's any improvements.

    I'll keep you informed of my findings

    Thanks !
  • Hi Emmanual,

    One other thing that would be good to check is you should see DOUT go high if you send 25 clocks.  This would show if the ADS1232 is responding to SCLKs.

    Best regards,

    Bob B

  • Thanks again Bob for your support,

    I tried 25 & 26 pulses on SCLK without any change...

    I also measured 100ns SCLK rise & fall time ( 50ns recommended in the datasheet).  However, I'm not sure how I could decrease this time since I'm directly connected to microcontroller's output.  (Could the slow rise & fall time be caused by my scope probe ? )

    Regards,

    Emmanuel

  • Hi Emmanuel,

    If you do not see DOUT/DRDY go high on the 25th clock, or an extended delay before the next DRDY after the 26th clock, then the ADS1232 is not seeing the SCLKs.  Can you get the scope probe directly on the SCLK pin of the ADS1232 and capture a shot of the scope so I can see what it looks like?  You will get an edge delay from the EMI filter.  The probe will add some additional capacitance, but is should be much less than the EMI filter cap.

    Sending me your board layout plots may indicate something as well.

    Best regards,

    Bob B

  • Thank you Bob,

    Here's a screenshot of SCLK rising edge. (2V/div, 100ns/div).   Falling edge identical.

    On this picture, EMI filters (100pF) have been jumped.  Probe (105pF) connected directly on ADS1232 pin #23

    And here's the layout

    Thank you very much for your help

    Regards

  • Hi Emmanuel,

    The scope probe is probably affecting the rise time as it seems a bit high for a scope probe.  Even if the signal looked the same without the probe you are probably ok as logic high is 0.7V*DVDD which is 3.5V for a 5V DVDD.

    I didn't see anything in the layout from preventing the data output, but I did notice that you have not effectively bypassed the supplies.  Bypass (or decoupling) caps should have the supply run across the cap and then to the device pin.  Also, you want a very low inductive path to ground on the ground side of the caps.  I also noticed that you have a lot of ground traces.  It is always best to tie the device ground pins with low inductance paths as well.

    So we are still left with the question as to why no data is output (or always stays low).  First let's start with what we do know.  We know that the device is getting power.  We also know that the device is functioning based on the DRDY pulses.  This means that the internal oscillator and digital is functioning.  What we don't see is any response due to SCLK.  It appears that the device does not see SCLK at all.

    A couple of possibilities exist.  One is the SCLK has a bad connection relative to the pin of the ADS1232.  This can happen from a cold solder joint, and sometimes by applying a little flux and reflowing the joint you will correct the problem.  Another possibility is the device was damaged either by an electrical overstress event (EOS) from handling or in soldering.

    If you have placed your probe on the pin of the package for the ADS1232 and you see the SCLKs, then I would try replacing the part.  Make sure that you adhere to the ESD information at the top of page 2 of the datasheet.

    Best regards,

    Bob B

  • Thanks for your help Bob,

    >>> I also noticed that you have a lot of ground traces. It is always best to tie the device ground pins with low inductance paths as well.
    So here's a question: can vias to GND planes be considered as low inductance path ?

    >>> Another possibility is the device was damaged either by an electrical overstress event (EOS) from handling or in soldering.
    You're probably right.

    What puzzled me regarding this issue is the fact the chip wasn't "completely" dead.
    I thought I may have missed something related to power-up and/or initialization sequence.

    Well, thanks for your help Bob, your help is invaluable

    Regards
  • Hi Emmanual,

    I'm glad that I can be of help in any way I can.  Hopefully replacing the part will solve the issue.  Sometimes an EOS event can affect the ESD cell in the device.  This can acutally open up a connection on the IC that can act as a fuse.  It is indeed interesting that your device seems to have no other issue associated with it.

    As far as vias and inductance, a via will have some inducatance associated with it.  A trace and a via will have even more than the via alone.  Using multiple vias can be more effective as the inductance is in parallel.

    You might take a look at the following for some further information:

    http://e2e.ti.com/support/data_converters/precision_data_converters/w/design_notes/1392

    Best regards,

    Bob B