Hello, all
Now we have some inquiries regarding ADS1672 from our customer.
Please refer to the items below, and feedback us with your comment.
1) When referring "TIMING REQUIREMENTS: Internal SCLK" on datasheet page 7, we could understand that the CLK duty cycle of Internal SCLK is in the range of 45 to 55%.
However, we could not find out about the case using external SCLK for serial data read. Please let us clarify whether we do not have to consider about duty cycle on this case.
2) When referring "Table 2. Noise Performance" on datasheet page 14, we could understand that each parameters on this table is based on fCLK = 20MHz.
However, since our usage on this device is fCLK = 6.5MHz, please let us clarify how these parameters would be changed on our case.
We thank you in advance for your information.
Best regards,