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Inquiries regarding hardware trim on ADS8506

Other Parts Discussed in Thread: ADS8506

Hello, all

Now we have some inquiries regarding hardware trim on ADS8506 from our customer.

Please refer to the item below, and feedback us with your comment.

Now we are designing our trial with using the configuration on "0 V to 5 V" of "Figure 42. Circuit Diagrams (With Hardware Trim)" which is described on datasheet page 21.

On this case, please let us clarify about the detail of this configuration as below;

1) Please let us clarify about the detailed relationship between the each components value and offset adjust range (+/-4mV).

2) Please let us clarify about the expected tolerance (%) of each components used on this schematic.

We thank you in advance for your information.

Best regards,

  • Hello Okui-san,

    I apologize for the delay, but here are my responses to your questions:

    1) The ADC input (Vin_ADC) is simply the superposition of three inputs, namely R1IN, R2IN and CAP. In other words,

    Vin_ADC = a1*R1IN + a2*R2IN + a3*CAP where a1, a2 and a3 are constants set by the resistor values

    Figure 42 shows two independent pot'meters for R1IN and CAP (0 to 5V range) and the input signal is applied to the R2IN input. The equivalent circuit is shown below (where R1 + R1 = R7 + R8 = 50kohm):

    The important thing to note is that any changes that POT1 and POT2 produce on Vin_ADC translate to changes in the ADC offset, and any changes that they produce on VCAP (which is the ADC reference voltage) translate to changes in the ADC gain.

    The principle of superposition can be applied to the circuit to isolate the effects of POT1 and POT2 on the offset (Vin_ADC) and gain (VCAP). To study the effect of POT1 on Vin_ADC, all other voltage sources are shorted to ground. Then using nodal analysis the following relationship is derived:

    Vin_ADC(R1,R2) = 3.71mV/(1+R1*(1/R2 + 1/1006k))

    For extreme values of the divider settings:
    Vin_ADC(0,50k) = 3.71mV
    Vin_ADC(50k,0) = 0

    Note that POT1 has no effect on VCAP because the buffer drives VCAP to 0V through a low impedance path.

    So VCAP(R1,R2) = 0 for all R1, R2

    Similarly, superposition and nodal analysis can be applied to study the effect of POT2 on Vin_ADC and VCAP:

    Vin_ADC(R7,R8) = 3.72mV/(1 + R7*(1/R8 + 1/33.399k))

    Again, for extreme values of the divider settings:
    Vin_ADC(0,50k) = 3.72mV
    Vin_ADC(50k,0) = 0

    For this case, VCAP is simply the buffered version of REF and can be expressed as follows:

    VCAP(R7,R8) = 29.2mV/(1+R7*(1/R8 + 1/1006k))

    For extreme values of the divider settings:
    VCAP(0,50k) = 29.2mV
    VCAP(50k,0) = 0

    Simulations are attached.

    POT1_DC_characteristic.TSC

    POT2_DC_characteristic.TSC

    2) As stipulated on page 22, 1% resistors should be sufficient.

    Regards,

    Harsha Munikoti

  • Hello, Munikoti-san,

    Thank you for your prompt reply.

    With regard to your explanation above, we have some additional inquires from them.

    Please refer to the items below, and feedback us with your comment.

    Based on the extreme values of the divider settings below, we could understand that the offset adjust range (+/-4mV) could be calculated as approximately 3.7mV * 2 = 7.4mV. (Since 3.7mV is middle point, we simply doubled this.)

    Vin_ADC(0,50k) = 3.71mV

    Vin_ADC(0,50k) = 3.72mV

    However, we could not understand how the gain adjust range (+/- 30mV) could be calculated from the extreme values of the divider settings.

    VCAP(0,50k) = 29.2mV

    Please let us clarify how we could understand this.

    We thank you once again for your information.

    Best regards,

  • Hello Okui-san,

    Compared to the "No trim" case shown in Figure 43, which is equivalent to having mid-range setting on the potentiometers (i.e, R1 = R2 = 25kohm and R7 = R8 = 25kohm), POT1 and POT2 can each provide upto +/-(3.7/2)mV of change in offset for a total offset trim range of +/-3.7mV.

    Similarly, for the gain trim range, POT2 can change CAP by +/-15mV (~= +/-29 mV/2 ) relative to the "No trim" case. Now, recall that to the outside world the ADC input range is 5V, but it is attenuated by 2x to a 2.5V range by the resistor network. So considering a gain of 0.5x, a 2.5 +/- 15mV ADC reference translates to (2.5+/-15mV)/0.5 = 5V +/- 30mV full-scale input range externally. Therefore, the gain trim range is +/-30mV.

    Regards,
    Harsha