AMC1210 / ADS1205 / External S/H race condition

Or - simplified - its not possible to use the tim reading to determine how many integration cycles have happened - if the external S/H is from a different time domain as the modulator clock.

Hi wolfgang,

I like this option best.  Is it possible for you to sync your ADS1205 devices (how many are you using) together on the isolated side?  If I read the first post correctly, you feed the outputs of your ADS1205 devices over an iso boundry to the AMC1210.  The ADS1205 can take an external clock, so if they are in close proximity to each other, you could potentially use the CLKOUT from one device to feed the other modulator(s).

Hi Tom !

Did you mean my last idea with "I like this option best" ? - using s&h mode and apply a filter reset at the start of every period ?

All channels are isolated individually, so a primary synchronization is not feasible.

We could run the AMC1210 with an 8MHz quartz oscillator, locked to the sampling clock - and provide the modulator clock over the iso barrier.

Question would be if there is a problem with the phase delay introduced by the isolator circuit. 

rgds.

Wolfgang

Hi Wolfgang,

Yes, S&H mode with a parallel reset - and you probably will see some phase differences with all the modulators clocking themselves.  If you could provide a common clock to the modulators, you may see some slight delay differences through your isolation, but I suspect it would be much less than what you see with them all clocking themselves.

Hi Tom,

Resetting the filter with integrator in S/H was no viable option - because we would need an additional integrator reset - and still suffered the problem that we cannot estimate the numbers of integrations derived from tim (this is needed because of frequency deviation of the self-clocking ads).

We finally decided to run without integrator at all - using 256times oversampling with the sinc3 filter. This gives us a jitter within +/-15us if we poll the last filter value from our sampleclock irq. So we run at 40kHz filter update rate and discard 90% of all updates - Because of a 400Hz LP on the input - this is no problem. We get rid of the artefacts caused by different time domain (which is 1.5% using SOSR32), now having few lsb variation@ 50% fullscale.

Additionally we have less delay - introduced by integrating the filter output - whats somehow interesting in our application.

Anyway - many thanks for your support. 

The AMC1210 datasheet is not too verbose - and there should be some warning notice what might happen if clocked as slave.....

Its clear now from technical POV what happens - otherwise there could be internal circuitry which circumvents certain unwanted phase condition between S/H and clock input - but its not.

rgds.

Wolfgang

Hi Tom,

On some AMC1210 - we have isolated multichannel inputs - means we have 2 or more ADS1205 with one acting as clockmaster.

So in this cases - we have the same modulator clock on all channels of this AMC1210.

If I would synchronize the common S/H signal with this incomming modulator-clock by means of some glue logic - it should be possible to circumvent that race condition.

For such a solution I would need some more informations about AMC1210 internals.

1) How many modulator cycles/edges does it take from rising edge of sample hold to an integrator reset ?

2) How many modulator cycles/edges does it take to transfer / add a new filter value to the integrator.

Both values determine the "blind" spot - which is responsible for the situation that the measured tim doesnt correspond to filter cycles in the integrator.

If 1+2 would happen on the falling edge of modulator input clock  - simple ANDing of S/H with modulator clock would be sufficient...

Is it possible to get more information regarding timing requirements of 1+2 if AMC1210 operated with external modulator clock ?

rgds.

Wolfgang

Hi Wolfgang,
Sorry for the delay in getting back to you. The integrator should be reset with the rising clock edge after S/H goes high. The filter value is transferred on the next falling clock edge. I'm not sure that a simple ANDing would be appropriate as you might end up with a glitch - using a flip-flop should get you synchronous to the modulator clock.

Hi Tom,

If filter values are added to the integrator at falling edge (which is independent from S/H)- and integrator gets reset at rising edge(after S/H)
there would be no problem at all.
a) if S/H happens slightly before rising edge - a new filter value was already added - or the next will be added at falling edge. no problem here.
b) if S/H happens slightly after rising edge - a new filter value was already added - or a last new filter value can be added on falling edge (is true ?)
So if your suggestions are true - I dont see a chance that a filter value gets eaten up (and thats my problem).
Somehow I think that the filter cycle ends with the falling edge/ data is latched - but is added to the integrator on rising edge.
This would lead to the situation where I miss one filter value.
So I conclude that there is no solution at all.
If the clocks are not synched - its not possible to avoid that filter output happens in same cycle as effective S/H.
If Integrator reset would be asynchronous - there would be the chance to delay S/H until rising edge occurs...

rgds.

Wolfgang

Hi Wolfgang,

The only asynchronous input pin on the AMC1210 is RESET - pin 37, everything else is dependent on the modulator clock. Is it possible for you to gate (turn off) the integrator/modulator clock until all filter modules are configured? From there, set MFE and then turn on the modulator/integrator clock?

Thanks, That makes sense.

Because there is no chance to change the hardware, we ended up using filter only - this gives more bits anyway.

rgds.