ADS1120 input filtering questions - Thermistors bridge

Hello Bob,

Thanks you very much for your prompt & detailed answer.

Please see some comments below.

Thanks again.

Bob Benjamin said:

Hi E L55,

See my responses below in RED.

Best regards,

Bob B

 

E L55

Hello, 

My application uses ADS1120 to perform high accuracy sampling of NTC thermistors differential bridge like figure 82 of the data sheet.

The Fixed resistors of the bridge are 39Kohm and the themisotrs change in the range 50-20Kohm depending on the temperature.

Sample is done once every minute in single-shot mode,  ODR is set to 20 SPS (in order to employ 50/60 Hz digital notch filter).

To reduce power PGA is bypassed (Gain=1) and Vref is turned on right before sampling  and then it turns back off (Vref connected to bridge's high side and REFP0)

LPF is implementation is Ccm=0.1uF, Cdiff=1uF, Rf=1K

Since the Bridge impedance is relatively high (Rmax= 39K || 50K ~= 22KOhm  -  Rmin=39K||20K ~=13K) I experience pretty long filter settling time >> 100 mS which leads to increased power consumption of the system.

I'm trying to design the minimally required filter.

I would appreciate if you could refer to the following questions :

1. Since the bridge is resistive, does Rf1/Rf2 resistors really needed ?
   BB> The bridge resistance will become a part of the antialiasing filter. However, you must consider the possibility that noise can be injected between the bridge and the input filtering caps which may limit the effect of the filter response.
   >> Is it something typical to long lines ?
2. Since ADS120 CMRR >90dB (15 bits, unipolar span), does it really need common mode filtering. Is there any CM noise aliasing concern ?
   BB> It is possible that the input filter created from the bridge can actually be unbalanced with respect to common mode and create a difference voltage. There is often little need for the common mode caps.
   >> I understand that bridge imbalance leads to unwanted differential signal (noise). But isn't it inherent to the bridge output? how its being mitigated by Ccm caps ?
   
3. In order to attenuate differential noise to <1LSB it has to be attenuated by 2^15 (15 'unipolar' bits resolution). Please confirm.
   BB> Yes and no. If the noise is not filtered by means such as the internal EMI filter or the digital filter, and the input noise is equal in magnitude to the signal, then you will be required to have extensive external filtering.  It most cases you will not need to have this kind of heavy filtering.  
   >> EMI filter cutoff is 31.8MHz (pg 45), digital filetring does not deal with aliasing ==>  so f_mod aliasing still requires external LPF, right ?
   btw, is EMI filtering presented when PGA is bypassed ?
4. Attenuation needed equals  to 20log(2^15)=90.3 dB
   ==> This attenuation translates to 90.3dB/(20db/dec)=4.5decades --> LPF cutoff should be 4.5 decades before f_mod --> f_cutoff= 125Hz
   ==> Cdiff=1/(2*pi*f_cutoff*Rmin) = 1/(2*pi*125*13K) ~= 100nF  (... 1/10th of current C_diff)
   ==> t_settle_max (to 1LSB) = ln(2^15)*Rmax*C_diff ~= 23 mS.
   BB> Notice figure 48 in the datasheet. At the 20sps data rate there is cutoff frequency at about 20Hz, with about -35dB or better throughout the remainder of the plot.  The big concern is aliasing which is discussed on page 44. You need to be +90dB down at the point of signals that can alias back into the passband.  Temperature change is near DC.  Aliasing of the signal rsponse becomes a small concern (what do you mean by 'signal aliasing'. Isn't the noise the one that 'aliases' ?).  However, noise within the passband can alias back, so as long as the noise component can be limited at the point of aliasing you should be ok.  The noise may already be significantly lower (say 50-60dB at the start) and will not require the full 4 to 5 decades.  This is where you need to know the environment your system will operate in and the potential noise sources that exist around the system. For example, let's say the noise is at 50dB down already, and you only need another 40dB at the modulator rate of 256kHz.  (oops, missed that. my calculation used 4.096MHz...)
   Here you can increase the cutoff frequency substantially to something around 2kHz so that the differential cap can be around 6-10nF.  Uncertainty for settling is 1/2 LSB, which is close to 11 time constants, and is about 78us in this scenario. However, if the noise potential is high, then you may need heavier filtering as you have demonstrated.
   >> What is a 'practical'  Noise level? Your calculation assume 50 dB down. If I understand correctly its 50 dB down compared to the ADCs full input span regardless of what this one is (or what gain is used). I mean it should be considered as absolute and not relative value. right ??
   Could you please confirm/correct  the filter design logic ?

Many thanks for your support.

Hi E L55,

See my continued answers below.

Best regards,

Bob B

E L55 said:

Hello Bob,

Thanks you very much for your prompt & detailed answer.

Please see some comments below.

Thanks again.

Bob Benjamin

Hi E L55,

See my responses below in RED.

Best regards,

Bob B

 

E L55

Hello, 

My application uses ADS1120 to perform high accuracy sampling of NTC thermistors differential bridge like figure 82 of the data sheet.

The Fixed resistors of the bridge are 39Kohm and the themisotrs change in the range 50-20Kohm depending on the temperature.

Sample is done once every minute in single-shot mode,  ODR is set to 20 SPS (in order to employ 50/60 Hz digital notch filter).

To reduce power PGA is bypassed (Gain=1) and Vref is turned on right before sampling  and then it turns back off (Vref connected to bridge's high side and REFP0)

LPF is implementation is Ccm=0.1uF, Cdiff=1uF, Rf=1K

Since the Bridge impedance is relatively high (Rmax= 39K || 50K ~= 22KOhm  -  Rmin=39K||20K ~=13K) I experience pretty long filter settling time >> 100 mS which leads to increased power consumption of the system.

I'm trying to design the minimally required filter.

I would appreciate if you could refer to the following questions :

1. Since the bridge is resistive, does Rf1/Rf2 resistors really needed ?
   BB> The bridge resistance will become a part of the antialiasing filter. However, you must consider the possibility that noise can be injected between the bridge and the input filtering caps which may limit the effect of the filter response.
   >> Is it something typical to long lines ? BB> EMI/RFI noise can be injected on long lines or short lines, but becomes more problematic with longer lines.  Using shielded cable or twisted pair cable can limit the noise on the cable relative to the inputs. 
2. Since ADS120 CMRR >90dB (15 bits, unipolar span), does it really need common mode filtering. Is there any CM noise aliasing concern ?
   BB> It is possible that the input filter created from the bridge can actually be unbalanced with respect to common mode and create a difference voltage. There is often little need for the common mode caps.
   >> I understand that bridge imbalance leads to unwanted differential signal (noise). But isn't it inherent to the bridge output? how its being mitigated by Ccm caps ? BB> You are correct, as the resistance is changing due to the design of the bridge.  Perhaps my short answer confused you so I will try again.  The common mode caps have little to no positive effect.  The more important cap is the differential cap.  To limit the effects of filter imbalance creating a differential voltage when common mode caps are used they must be significantly smaller in value as compared to the differential cap.  In many cases this would be a minimum of the common mode caps being 1/10 the value of the differential cap.   
   
3. In order to attenuate differential noise to <1LSB it has to be attenuated by 2^15 (15 'unipolar' bits resolution). Please confirm.
   BB> Yes and no. If the noise is not filtered by means such as the internal EMI filter or the digital filter, and the input noise is equal in magnitude to the signal, then you will be required to have extensive external filtering.  It most cases you will not need to have this kind of heavy filtering.  
   >> EMI filter cutoff is 31.8MHz (pg 45), digital filetring does not deal with aliasing ==>  so f_mod aliasing still requires external LPF, right ?  BB> The digital filter does not emliminate the need for an antialiasing filter but rather relaxes the requirement to a first order RC filter in most cases (as opposed to a multi-pole active filter). 
   btw, is EMI filtering presented when PGA is bypassed ? BB> The EMI filter is primarily for the PGA.  From the design documentation it is difficult for me to say exactly where the switches are for the bypass relative to the filter, but I would assume that the filter is not in circuit when the PGA is bypassed.    
4. Attenuation needed equals  to 20log(2^15)=90.3 dB
   ==> This attenuation translates to 90.3dB/(20db/dec)=4.5decades --> LPF cutoff should be 4.5 decades before f_mod --> f_cutoff= 125Hz
   ==> Cdiff=1/(2*pi*f_cutoff*Rmin) = 1/(2*pi*125*13K) ~= 100nF  (... 1/10th of current C_diff)
   ==> t_settle_max (to 1LSB) = ln(2^15)*Rmax*C_diff ~= 23 mS.
   BB> Notice figure 48 in the datasheet. At the 20sps data rate there is cutoff frequency at about 20Hz, with about -35dB or better throughout the remainder of the plot.  The big concern is aliasing which is discussed on page 44. You need to be +90dB down at the point of signals that can alias back into the passband.  Temperature change is near DC.  Aliasing of the signal rsponse becomes a small concern (what do you mean by 'signal aliasing'. Isn't the noise the one that 'aliases' ?).  However, noise within the passband can alias back, so as long as the noise component can be limited at the point of aliasing you should be ok.  The noise may already be significantly lower (say 50-60dB at the start) and will not require the full 4 to 5 decades.  This is where you need to know the environment your system will operate in and the potential noise sources that exist around the system. For example, let's say the noise is at 50dB down already, and you only need another 40dB at the modulator rate of 256kHz.  (oops, missed that. my calculation used 4.096MHz...)
   Here you can increase the cutoff frequency substantially to something around 2kHz so that the differential cap can be around 6-10nF.  Uncertainty for settling is 1/2 LSB, which is close to 11 time constants, and is about 78us in this scenario. However, if the noise potential is high, then you may need heavier filtering as you have demonstrated.
   >> What is a 'practical'  Noise level? Your calculation assume 50 dB down. If I understand correctly its 50 dB down compared to the ADCs full input span regardless of what this one is (or what gain is used). I mean it should be considered as absolute and not relative value. right ??  BB> The noise, the input signal and the data rate all have the potential to alias back into the pass band.  As far as an answer to a practical noise level this is difficult to answer.  It will vary greatly depending on the circuit and operating environment.  Ideally the noise will be 0.  For building the filter, you need to look at what are the most important factors.  It appears that settling time is highly important.  If this is true, then why not work backwards to get the best filter for the required settling.  I used 50 dB justs as an example.  It is totally arbitrary on my part to show that you may not need as much filtering is you are calculating.    
   Could you please confirm/correct  the filter design logic ?

Many thanks for your support.