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ADS1271 - SPI serial interface, restarting conversion problem

Other Parts Discussed in Thread: ADS1271

The ADS1271 datasheet page 25 tell us
For the fSCLK/fCLK ratio of 1, care must be observed that these signals are not tied together. After Power On, SCLK remains an output until a few clocks have been received on the CLK input.

Here are my steps
(1) power on ADS1271
(2) separate CLK and SCLK pins (with switch)
(3) FORMAT pin state is determined (SCLK, input)
(4) tied CLK and SCLK together
(5) ADC start conversion
(6) hold low for PDWN pin to place the ADS1271 in power down mode

And my question is
Before restarting conversion (pull high the PDWN pin), do I need to separate CLK and SCLK pins again?

Thanks in advance.

Ben Tan

  • Hi Ben,

    CLK and SCLK are not usually tied together. Typically, these clock signals are produced by the same clock source within an FPGA or other processor. This allows the user to configure two independent clocks that are a multiple of one another but still in phase. You do not need to send SCLKs until the device is ready to output valid data.

    I suppose to answer your question more directly - yes, you would need to separate the clocks again when you bring the device out of power-down. SCLK will initially be configured as an output.

    Best Regards,