The ADS1271 datasheet page 25 tell us
For the fSCLK/fCLK ratio of 1, care must be observed that these signals are not tied together. After Power On, SCLK remains an output until a few clocks have been received on the CLK input.
Here are my steps
(1) power on ADS1271
(2) separate CLK and SCLK pins (with switch)
(3) FORMAT pin state is determined (SCLK, input)
(4) tied CLK and SCLK together
(5) ADC start conversion
(6) hold low for PDWN pin to place the ADS1271 in power down mode
And my question is
Before restarting conversion (pull high the PDWN pin), do I need to separate CLK and SCLK pins again?
Thanks in advance.
Ben Tan