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ADS1278evm-PDK Format Pin error

Other Parts Discussed in Thread: ADS1278, ADS1278EVM-PDK

Hi,

Currently I'm trying to use SPI to communicate to an SPI - USB bridge that interfaces with LabView. Seeing the datasheet, for SPI communications the Format [2:0] pins should be in the range of 000-010... yet, for some reason, the Format [2] pin is always in a high logic level even when not connected to the SPI-USB bridge. Seeing this, I verified that the DIP switch S2 was set downwards, so it is connected to ground, but changing the switch from up to down does not change the logic level, it is always high.. so it is always configured as Frame Sync. When I change the position of the dip switch for other pins, they work properly... so my thought was that the dip switch was malfunctioning, so I removed it, hoping to solve the issue, but the result was the same. 


I've checked the schematic and the Format pins are connected to the pull-down resistance, the dipswitch and then to the ADS1278, being the dip switch the apparent connection to the IOVDD... is there another connection from the Format pin to IOVDD that I'm missing? what other reason could there be to the high logic value of that specific pin? As a last resort I'm thinking of directly connecting the Format 2 pin to DGND, as I'm not interested in frame sync comms, but I would appreciate another better solution.


Thanks

  • Hi Carlos,

    Welcome to our forum and thank you for bringing this to our attention!

    I was able to reproduce the same issue on my bench when I was not using the provided software. These pins were designed to be pulled low through 100k resistors while the dip switch is in the down position. It seems that FORMAT[2] is finding a path to IOVDD, possibly through the I2C port expander (U7), as soon as the PDK is powered on, even without the software.

    The EVM GUI is still able to pull this pin low when the output data format is configured for Frame-Sync, TDM, Dynamic Mode, but I understand that you wish to configure the device for SPI. I will continue to look into this issue and provide a solution as soon as one is available.

    Best Regards,
  • Hi Ryan,

    I've tried connecting the FORMAT[2] pin to DGND and indeed I see a logical 0 on the ADS1278 pin 30, yet I'm not able to make a succesful SPI transfer... shouldn't it be working? From what I understand from the datasheet, there is no specific sequence I should follow like when syncing and mode changing.

    Another question... upon startup, should I make sync first and the change mode? Right now I Sync, change mode and try to get data from SPI, is this the correct sequence? or should I do the mode change, sync and afterwards spi transfer. 

    Regards,

  • Hi Carlos,

    Are you still using the firmware and GUI provided with the ADS1278EVM-PDK? The PDK does not support SPI Mode and any changes you make to it cannot be supported from our side.

    The SYNC pulse is only necessary if you wish to synchronize multiple ADS1278 devices to the same clock cycle or if you need to reset the digital filter following some external event (i.e. changing an external multiplexer).

    When you change the Mode[2:0], the ADS1278 conversions will stop and the digital filter will reset. The required settling time is a maximum of 129 data rate periods. Pulsing the SYNC pin would only add an additional settling time delay. You can refer to Figure 72 in the datasheet to see how /DRDY indicates when new data is ready after a mode change.

    Best Regards,
  • Hi Ryan,

    I'm not using the GUI from TI, I have my own interface with Labview and interface the PDK with an SPI to USB bridge. Just to clarify, the ADS1278EVM-PDK doesn't support at all SPI mode? even if I change the S6 from FSYNC to SPI and extracting the data from D1OUT?

    Thanks for your reply.

    Regards,

  • Hi Carlos,

    The ADS1278EVM can use SPI Mode as long as you have connected the daughterboard to a processor that can support SPI. The firmware for the ADS1278EVM-PDK (which uses the MMB0 platform with a C5509 DSP) does not support SPI Mode as-is.

    If you flip S6 to the "SPI" position, the SPI pins of the ADS1278 will be connected to the J4 header according to Table 8 in the User Guide (please excuse the "J5" typo).

    Best Regards,
  • Hi Ryan,

    Currently I'm using the MMB0 board only to power the ads1278 evm and using the J4 for all my SPI, format and mode configuration. My main concern is with that faulty pin,  as I'm not sure it is being properly  configured  so that Spi  will work.

    Regards

  • Hi Carlos,

    It is not the pin on the ADS1278 that is faulty - instead, this pin is being controlled by the firmware loaded on the MMB0 by default. You should be able to disconnect the FORMAT[2:0] pins on J4 from the MMB0 and control them manually with a wire to IOVDD or DGND. Then you can probe the ADS1278 pins to confirm that the setting is valid.

    Regards,