TLV2542 Reset the MUX to AIN0

Hidekazu Fujikawa

Intellectual 460 points

Other Parts Discussed in Thread: TLV2542

Hello,

In using TLV2542, I can't confirm to reset the MUX to AIN0.

Please teach me the condition to reset without fail.

The attached is our timming chart.

- SCLK = 1MHz

- /CS = 5-CLK cycle LOW --> 2-CLK cycle HIGH (for Toggle AIN0 to AIN1) --> 22-CLK cycle LOW (for Conversion) --> 2-CLK cycle HIGH (for Toggle...)

- Expect SDO = ch1 OUT --> ch0 OUT --> ch1 OUT --> ch0 OUT .....

BUT, in our device actual output is: ch0 OUT --> ch1 OUT --> ....

- SCLK = 1MHz

- /CS = 7-CLK cycle LOW --> 2-CLK cycle HIGH (for Toggle AIN0 to AIN1) --> 22-CLK cycle LOW (for Conversion) --> 2-CLK cycle HIGH (for Toggle...)

- Expect SDO = ch1 OUT --> ch0 OUT --> ch1 OUT --> ch0 OUT .....

BUT, it was the same result as above.

- SCLK = 1MHz

- /CS = 5-CLK cycle LOW --> 3-CLK cycle HIGH (for Toggle AIN0 to AIN1) --> 22-CLK cycle LOW (for Conversion) --> 3-CLK cycle HIGH (for Toggle...)

- Expect SDO = ch1 OUT --> ch0 OUT --> ch1 OUT --> ch0 OUT .....

In this case, we could get the expected results.

1) Why it has been reset the MUX to AIN0 by the /CS High of 3-CLK cycle?

2) What is the condition to reset surely?

3) What is the condition to toggle the AIN? (How many CLK cycles dose it need to toggle?)

Best Regards,

H. Fujikawa

1817.TLV2542_TimmingChart.xlsx

over 8 years ago

0 Sandeep Kasargod over 8 years ago

TI__Expert 4405 points

Fujikawa-san

As mentioned in the TLV2542 datasheet on page5, a dummy conversion cycle after power up is recommended before attempting to reset the MUX.

Could you please confirm that this has been done, before each of these tests were conducted?

Thanks.

Regards,
Sandeep

0 Hidekazu Fujikawa over 8 years ago in reply to Sandeep Kasargod

Intellectual 460 points

Sandeep-san,

Thank you for your reply.

We tried to insert a dummy conversion cycle, but it did not go well.

Even after repeated many times reset, SDO is always Ch0 and Ch1 is output in reverse order.

(Reset is working, but the order of the output is reversed.)

Do you see that there is an error in our timing chart Fig1-4?
If Fig4 is OK, /CS Low needs 3CLK Cycle to toggle?

Thank you.
Best Regards,
H. Fujikawa

0 Sandeep Kasargod over 8 years ago in reply to Hidekazu Fujikawa

TI__Expert 4405 points

Fujikawa-san,

Sorry about this delay in responding.

I managed to talk to one of the designers of this part today and he confirmed that the MUX reset functions as expected. As mentioned in the datasheet, a 4 to 7 SCLK wide CS cycle resets the MUX to Ch0. And a greater than 7 SCLK cycle toggles the MUX to the next channel.

We reviewed your timing diagrams together to try and figure out what might be going wrong.

The timing in Fig 4 would always pass, since it is well within the 4-to-7 SCLK limit for CS low. The CS high of 3 SCLKs does not matter.

With Fig 3, the device might actually seeing 8 edges instead of 7 edges, which is why it fails. A oscilloscope capture of the CS low period along with SCLK would confirm this. Alternatively, we could try a 6 SCLK CS low period to check this.

Regards,

Sandeep

0 Hidekazu Fujikawa over 8 years ago in reply to Sandeep Kasargod

Intellectual 460 points

Sandeep-san,

Thank you for your confirmation.

According to "The CS high of 3 SCLKs does not matter.", I could see our Fig 2 is not wrong too.

However, the results of our experiments, the /CS Hi of 3-CLK (Fig 4) is passed, the /CS Hi of 2-CLK (Fig 2) is failed.

So I'd like to know the RESET mechanism, could you tell me in simple?

- Does it has a circuit to set the MUX to AIN0, after discharge S/H capacitor by 4-to-7 CLKs /CS Low?

If it has such a circuit, we suspect that it is broken by EOS of our application.

Thank you.

Best Regards,

H.Fujikawa

0 Sandeep Kasargod over 8 years ago in reply to Hidekazu Fujikawa

TI__Expert 4405 points

Fujikawa-san,

I can confirm again, that the reset sequence that you have described is perfectly correct.

After power up, one dummy cycle is required to reset the internal state machine and the first output data could be from either channel. A 4-to-7 CS low cycle sets the MUX to AIN0, and the second output should correspond to the AIN0. Any greater than 7 CS low cycle, toggles the MUX to the next channel. The CS high period is of no significance, as reconfirmed by the designer.

It is very unlikely that this internal reset circuit could be damaged by EOS damage. But this raises several questions – how many parts are showing this behaviour? Is this a new design or is it an existing design that is misbehaving on one or more boards? Does replacing the part solve the problem? Please provide details of the design and customer.

I agree with your observation that Fig 2 should have passed, but it would really help if we can see a oscilloscope capture of the fail condition to debug this further.

Thanks.

Regards,

Sandeep

0 Hidekazu Fujikawa over 8 years ago in reply to Sandeep Kasargod

Intellectual 460 points

Sandeep-san,

I'm sorry for my late reply.
Thank you so much for your kindly support!

> - How many parts are showing this behaviour?
TLV2542 x 1pcs on this board/system.
Now, we could confirm 3pcs (3-board) failure out of 50-60 boards.

> - Is this a new design or is it an existing design that is misbehaving on one or more boards?
It is an existing design.

> - Does replacing the part solve the problem?
We can not yet. It is under investigation in the external manufacturing plant.

> - Please provide details of the design and customer.
When I get the additional information, please let me have a consultation by e-mail.

Thank you.
Best Regards,
H.Fujikawa

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TLV2542 Reset the MUX to AIN0