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AMC7820 SPI CLOCK Rist time

Jovin Basil
Prodigy 130 points
Other Parts Discussed in Thread: AMC7820

I am using AMC7820 for one of my projects.In that i have 24 AMC7820 IC's used in parallel.I would like to know about the SPI clock rise time required.The speed of SPI used in the project is 1.5MHz.

The Voltages being supplied are AVDD=DVDD= 5V and BVDD =3.3V.


In the table,page 6,its specified that maximum rise time is 30ns.So does that mean that for 1.5MHz clock signal,the rise time should be less than 30ns.If the rise is greater than that,for eg for 1.5MHz if rise time is 100ns,will that cause any problem to the IC or any other functionality?


I would also  like to know whether the rise time required for each clock frequency can be different or should always be less than 30ns?

  • 0
    TI__Genius 11750 points
    Howdy Jovin,

    The 30ns Max Rise/Fall time spec applies to any acceptable SCLK freq, as well as any other digital signals.

    If the Rise/Fall time is greater than the value listed you will more than likely get degraded timing performance, and the digital lines may be more susceptible to any external noise.

    Regards,
    Matt
  • 0 in reply to Matthew Sauceda
    Prodigy 130 points

    Hi Matt,

    Thanks for your reply and Sorry for the late response.

    If i make the rise time of Clock and MOSI the same ie for eg 100ns will there be still the degraded timing performance or any external noise?

    Also if i decrease the clock frequency to 375Khz,is it possible to increase the rise time based on the clock frequency?

    Whether the specified rise time of 30ns is for a particular frequency or is it for the whole range of frequency from 1KHz to 30MHz?

    Regards

    Jovin

  • 0 in reply to Jovin Basil
    TI__Genius 11750 points
    Howdy Jovin,

    The 30ns max rise time applies to the full frequency range (1kHz-30MHz).

    Some microcontrollers/processors have the option of increasing the current drive of I/O pins, this will help decrease the rise and fall time of the digital signal enabling you to meet the criteria specified in the datasheet.

    Regards,
    Matt
  • 0 in reply to Matthew Sauceda
    Prodigy 130 points

    Hi Matt,


    So 30ns rise time means we can have a minimum of 1ns and a maximum of 30ns rise time.

    So if the rise time is 1ns ,that means the maximum frequency is 1/1ns ,ie 1GHz.

    So for a clock frequency of 375KHz or 750KHz,does it really need a clock rise with 1GHz?This can add more overshoot and noise.Am i correct?

  • 0 in reply to Jovin Basil
    TI__Genius 11750 points

    Hello Jovin,


    Yes you are correct, the faster the rise and the fall, the more likely overshoot and undershoot would occur.  External noise would not couple into the digital lines as much as they would be driven with a larger current source in meeting the faster rise and fall times.  It is best to drive around the maximum rise and fall value of 30ns.

    Best Regards,

    Matt