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ADS1293 Analog AC Lead-Off Detection

Other Parts Discussed in Thread: ADS1293

Hello,

I'm trying to adjust the Analog AC Lead-Off detection with the ADS1293, and I'd like more explanation than what's written in the datasheet. More specifically about the Threshold levels and the way the AC voltage is measured in each input.

I'm configuring the following registers:

LOD_CN                 0b00010100           /* Lead Off Detect ON, AC analog, level 1 */
LOD_EN                 0b00100000           /* Lead Off Detect ON in IN6 */
LOD_CURRENT   175                           /* Lead Off Detect Current is i_lod = 175*8nA = 1,4uA */
LOD_AC_CN         19                             /* AC Lead Off Detect frequency: K = 1, ACDIV_LOD = 19 -> freq = 625Hz */

When the datasheet says (8.3.17, page 26):

"The resulting AC current has a frequency Φ and a peak-to-peak amplitude equal to the current programmed into the DAC. An AC coupled synchronous detector detects the amplitude of the AC voltage appearing on the lead. The detected amplitude is compared to a reference voltage by means of a Schmitt-trigger comparator."

My questions are:

1) The detector detects peak amplitude? peak-peak amplitude? or what amplitude measurement of the voltage? I'm asking this because I have to choose the threshold level according to the type of measurement.

2) The peak-peak voltage that should appear on the input IN6 is exactly the product of the peak-peak current set (1,4uA) and the resistance between that input and ground (or some low impedance point such as RLD)? Because I measure exactly twice of the value that I calculate.

3) If the detector detects peak-peak voltage, can it handle a waveform that is not square? I'm asking this because there's an impedance between the input and ground that is not purely resistive. For EMI reduction purposes there is a capacitor from the input to ground, and the waveform gets distorted to a triangle shape.

Thanks,

Gustavo

  • To answer your questions, I would need to double check some archived design documentations, I will get back to you  with the answers soon. 

  • Answer to Q1 &2: the detector consist of a high pass filter, a synchronous detector, a low pass filter and a sample and hold (SH) connected to a comparator. As the SH output voltage ramps up based on the impedance change, it is compared to the output of the reference DAC programed by the user.  the programmable reference levels at the two VDD supply are, that is what you should see at the output:

    ACLVL_LOD   [1:0] VDD = 2.7V VDD = 5V
    0 1.6V 3.0V
    1 1.8V 3.4V
    2 2.0V 3.8V
    3 2.2V 4.2V

    Answer to Q3:  As I mentioned above the signal at the input of the detector's comparator  is a ramp generated from demodulating, filtering, and integrating the input signal. It should work with a triangular waveform. I do not have access to the validation data from 4 year ago and you should be able to confirm it using your setup in the lab. 

  • I am attaching the source data for FIGURE 24 in the datasheet, and the same graph but with the logarithmic sub-grid enabled. For example, with an excitation frequency of 2kHz, the threshold voltage levels are:

    Level 1 ≈ 21mV

    Level 2 ≈ 54mV

    Level 3 ≈ 90mV

    Level 4 ≈ 140mV