ADS1299, DOUT hold time, conflicting informations in data sheet

Hi Brian,

Thanks a lot for a lightning fast reply.

But are you positive that this is the page 34 which is incorrect?

An output that is updated on the rising clock edge and then made invalid on the falling clock edge would made for a very strange SPI indeed.

As comparison:
ADS1255 data sheet, page 6:
"SCLK _rising_ edge to valid new DOUT: propagation delay"
"SCLK _rising_ edge to DOUT invalid: hold time"

Or, from the data sheet of a device from my favourite microcontroller family with a very good SPI (thanks TI :) )
MSP430F5529 data sheet, Figure 13 & 14 page 68,
both "tHD,SO SOMI output data hold time", and "tVALID,SO SOMI output data valid time" are anchored at the same clock edge.

The standard story in digital design is:
if an output is clocked with (let say) rising clock edge:
- the output would hold the previous value stable for the "hold" (tH) time after rising clock edge,
- then the signal is changing (the value is "undefined")
- and at the "output delay" (tCO) time (from the same rising clock edge) the output becomes stable with the new value.

To make an output that changes value on one clock edge and changes it again on the opposite edge, one would need two FFs (one of them with inverted clock) and some combinatorial logic ...
Is this really what has been done with DOUT output in ADS1299?

Thanks,
Pawel

Hi Brian,

Sorry for being so picky, but, if "Timing Requirements" table is not correct, and t_DOHD should be measured from the rising edge of SCLK, then the current text on page 37 is likely to be correct.

Let me explain:
DOUT output is updated shortly _after_ the rising edge of SCLK.
DOUT change is not instantaneous, and the previous value remains stable for some time after the SCLK edge.
(if timing table is updated then: DOUT value remains stable for at least t_DOHD after the rising SCLK edge)

Therefore capturing DOUT on the rising edge is fine, as long as "stable time" on DOUT is greater or equal to t_HOLD required on the input.

Output Hold time on DOUT: t_DOHD = 10 ns
Input Hold time required on DAISY_IN: t_DISCK2HT = 10ns

Running with output hold time equal to input hold time makes it highly sensitive to timing, but this is what is hinted on page 37:
"... also makes the interface sensitive to board-level signal delays."
"... the more challenging it could become to adhere to setup and hold times."

To summarise:
- The current description of t_DOHD in "Timing Requirements" table looks suspicious (and, among others, if does not match description and timing diagrams on page 37
- If the "Timing Requirements" table is changed then data sheet becomes consistent

Of course, this needs to be checked against the actual design.
There is a slight chance that DOUT output circuit has actually been made in such unusual way ...

Thanks a lot for your support

Regards,
Pawel