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lower data rates with ADS130E08 or ADS131E08 (eg: 500 sps)

Gil Smith
Prodigy 80 points
Other Parts Discussed in Thread: ADS130E08, ADS131E08, ADS1298

Hi folks:


I wish to use a lower data rate with ADS130E08 or ADS131E08 (eg: 500 sps) than the devices allow.


I realize that I could start and stop the converters at a rate of my choosing, but I was wondering whether I could just leave them in continuous mode and only grab data every N cycles of DRDY? 

For example, if the 131 is running continuously at its minimum 1000sps, can I just get data every second DRDY?  I presume the output regs just get overwritten an the end of each conversion.  Likewise, for the 130 which can only be throttled down to 8000sps, can I just grab every 16th occurrence of DRDY?


I am very familiar with the spi access to these devices as they appear identical to the 129x parts for which I have written production code.


thx, Gil

  • 0
    TI__Mastermind 23235 points
    Hello Gil -
    Depending on the datarate you wish to receive, you can adjust the master clock (CLK) input frequency (using external clock source) to reduce the datarate. Ensure that you stay within the datasheet limits for the clock frequency.

    As you mentioned, you can certainly use only the data that you want; ie skipping measurements as you described. However, be aware that skipping measurements does not equal the same datarate. If you want the data just for reference/instant measurement, this is OK. However if you plan to use this data for analysis (for example a FFT), you really should have contiguous data.
    Alternatively, you can just further decimate the received data down to the desired frequency of interest. This is a pretty common operation of the devices by our customers who wish to do their own decimation/filtering.
  • 0 in reply to Greg Hupp
    Prodigy 80 points
    Hi Greg: Thanks for the speedy reply.

    I thought about using a lower ext clock (even though it adds a part or an int routine). Using a 1.024 MHz ck instead of 2.048 should give me 500sps instead of 1000sps.
    However, for the ads131 in which I have the most interest, the ext clk min is 1.7 MHz at 3V and 0.7 meg at 5V -- as I will be running at 3.3V, it looks like 1.024 MHz would be out of spec (or just barely).

    Why is it that skipping every other measurement (whether I actually read it or ignore the DRDY) does not really give me half the data rate? Let's say I use the ads131 at supported rates for an example: I acquire at 1000sps on a test signal and do an fft. Then I run the adc at 2000sps, skipping every other data point, and do an fft. Would they not be they the same or am I missing something?

    Can you point me to a reference on doing the additional decimation?

    thx, gil
  • 0 in reply to Gil Smith
    Prodigy 80 points
    Hi Greg:

    I realize the alias foldback implications -- to clarify my downsampling question: I am presuming that the input before higher-rate sampling is already bandlimited to less than 1/2 the final sample rate. Is the non-decimated half-rate data not the same in this case?

    thx, gil
  • 0 in reply to Gil Smith
    TI__Mastermind 23235 points
    Hello Gil -
    In terms of skipping data points, as mentioned previously, if you are strictly interested in periodic measurements, this plan will probably be acceptable. For detailed analysis/performance, this plan may not provide the best option. As you noted, aliasing can be an issue that is often overlooked in terms of system signals that are coupled in. By using higher data rates, you are also not getting the best noise, SNR, etc. since that is gained through the increased OSR values of the ADC. It is a trade-off of performance vs convenience in your design.
    If you want a slightly reduced datarate, you might check out ADS1298. While the primary market for the device is medical, it is still a generic ADC that allows you to get a lower datarate directly from the ADC. There are also different resolution and channel variants of this ADC.