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ADS1262 : CS and DRDY

Other Parts Discussed in Thread: ADS1262

Hi,

I'am writing firmware for ADS1262 and i don't understand §9.4.4.1 of data sheet :

"When CS is high, the serial interface is reset, SCLK input activity is ignored
(blocking input commands), and the DOUT/DRDY output pin enters a high-impedance state."

and just after :

"The DRDY output asserts low when conversion data are ready and is not affected by CS."

Can i use DRDY for interrupt if CS already returned Hi state ?

thanks for your help

         Hervé

  • Hi Hervé,

    /DRDY will go low to indicate that a conversion has completed, even when /CS is high. This allows the MCU to perform other tasks or communicate with other devices on the SPI while waiting for the conversion to complete.

    When /CS goes high, the ADS1262 will disregard any commands in progress. Toggling /CS allows you to re-synchronize SPI communication (i.e. in the case that a glitch occurs on the SCLK signal, causing the ADS1262 to read an unintentional value).

    I hope that helps!

    Best Regards,
    Chris

  • Hi Hervé,

    To add to my last comments... there are two /DRDY signals. One comes from a dedicated "/DRDY" pin and the other from the multifunction "DOUT/DRDY" pin.

    The dedicated "/DRDY"pin will go low when a conversion completes, regardless of the state of /CS.

    However, the "DOUT/DRDY" pin will be high-impedance when /CS is high. Therefore, /CS will need to be low if you plan to monitor the state of /DRDY from this multifunction pin. The main reason for providing this multifunctional pin is to be able to use fewer digital signals in cases where digital isolation is required.

    Best Regards,
    Chris
  • Thank you very much, Christofer.

    I think i made confusion between two different pins : DRDY et DOUT/DRDY

    Best Regards

    Hervé