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ADS1256 Self Calibration Problems

Other Parts Discussed in Thread: ADS1256, OPA350, ADS1255

Hi:

I have made ADS1256 almost working fine, except the self calibration.

First, I was to confirm:
1. I use AIN2 as AINP and AIN1 as AINN, is that correct? They are adjacent inputs, datasheet page 14.

2. I use 2 ADS1256s, which share SCLK, DIN, DOUT and VREF, other function pins DRDY and CS are seperatly controlled.
    The VREF circuit follows what in the datasheet fig. 16, except that 1 OPA350 drives 2 ADC parts, with 100+47uF titan capacitors, without 49.9ohm resistor. The circuit is the same with EVA board, but 1 OP drives 2 ADCs.
    Can they run correctly?

3. The init sequence 5 second after power up is:
        Wait for DRDY=0;
        Send Command RESET; wait for DRDY=0;
        Send Command SDATAC; wait for DRDY=0;
        Write Reg STATUS 0x02, for ACAL OFF, BUFFER ON.wait for DRDY=0;
        Write Reg MUX 0x21, for AINP=AIN2, AINN=AIN1;wait for DRDY=0; (AINP=AIN0, AINN=AIN1 for the second part)
        Write Reg ADCON 0x22, for SDCS OFF, PGA=4;wait for DRDY=0; (PGA=16 for the second part)
        Write Reg DRATE 0x63, for 50SPSwait for DRDY=0;
        Write Reg IO 0x01;wait for DRDY=0;
        Send Command SELFCAL;wait for DRDY=0;
    For each ADS1256, init sequence above is used. Is this sequence right?

And, here are the phenomenan:

1. SELFCAL result changes.
    Each time when ADS1256s are powered up, and, after about 5 second, initialized one by one, I read back the OFC and FSC registers, they will change each time.
    I notice that FSC will change if OFC changes, and with same OFC values, FSC varies little, about 4-6 LSB.
    For the first part, I find some OFC values usually appear, say FFEF1F and FFEFBF, by chance, which affact the reading. Other values are near around these 2 values, but there are some other values, even they are not usually occur.
    At first, I doubt that the power up procedure will affect the self calibration, i.e. the reference voltage and supply voltage. So, I program the MCU to init the parts every 5 second following the above init sequence, and then read OFC and FSC registers, a long time after power on. The phenomena is same.
    And I also find that with time passed, after periodically init, OFC changes much, say from FFEF1F and FFEFBF to FFECA3 and FFED3F, about 636 LSB or 0x027C, but the difference of usually occuring values is about 160 LSB, or 0xA0.

   
2. ACAL turn on
    Then I turn on ACAL in STATUS register, after power up, both of them refuse to change DRATE to 4, it remains 30k, so I think other settings do not work too.
    Initialization every 5s also has no effect. Thet still output DRDY at 30kHz. In every 5s init, OFC and FSC also change, say OFC=FFFFFF or FFF120 or some other values, FFFFFF appears more, I think these values are of no sense since the DRATE is wrong.

3. SELFCAL when short input terminals
    So, I have to use SELFCAL command to calibrate them, but this time I short the input terminals, because I think input signal will disturb the calibration procedure, the phenomena is similar. OFC changes to FFEF1F or FFEE7F. And I find that the reading is not near 0 or FFFFFF, it is FFFCxx. So calibration seems not work correctly.

4. SELFCAL on unused inputs
    Calibration is to connect input to VREF and 1/2VDD internally, input signals will not disturb calibration in theory. Even so, to avoid any disturbing, I use unused floating inputs for calibration, say AINP=AIN6 and AINN=AIN7, phenomena is similar, but OFC=FFEF1F occurs more.

--------------------------------
Why the OFC alters after SELFCAL command, and at the same time, short input readings are not near 0, even with floating input terminals? And why OFC havs some fixed values.
Why the OFC changes so much, 636 LSB is not acceptable in my circuit.
Why ACAL does not work? Are there any operations not correct in Init procedure?
--------------------------------

    I have monitered and waited for DRDY falls to 0 before and after every operation, including RREG, WREG, RDATA, SDATAC, SELFCAL, RESET, to start the next operation.

    I can read readings, write and read registers correctly, except ACAL ON.

    I have seperated analog and digital ground, and confirmed no jitter or digital current in analog ground. The deltaV between these two ground planes is lower than 100uV, measured by K2000 in fast mode with filter off.

    I have seriously dealt with signal and ref tracks, and they work well. The parts now work very well if I ignore the offset and gain error (I think FSC is correct, but OFC is not), and they can almost reach the specifications in datasheet.
    
    Because I ever wanted to use SYNC/PWDN and RESET (but I ignored t16 ^-^), these 2 pins are not directly connected to 3.3V VDD, but output terminals of a 74HC14, but they are set HIGH levels by MCU, immediately after power up, about 5s before init procedure begins.

    Digital signals are isolated by several optocouplers of HCPL-M611, and I have check the waveform, they works correctly.
    


    And I was some confused by the datasheet. The information "the part will enter RDATAC state after power up" is not mentioned, and the formula (3) in page 24 has no clear statement, I cannot calculate the correct output from the formular with OFC and FSC. I would also like to suggest that an offical init procedure can be provided in the latest datasheet, I found so many problems about inits in the forum.

regards.


  • Hi.

    I notice in datasheet page28 that, digital and analog ground is recommended to be a single plane, and if use a split ground, difference between them is not allowed.

    This is unique for converters which have seperated defined ground pins.

    I have seperated digital and analog ground in different planes, and they are finally connect to one point. Before this point, digital plane passes through a region in which there are 10 optocouplers, each of them will produce 7mA pulse current. That will be the source of AC voltage difference between digital and analog ground level. The DC defference is ignored, it is less than 10uV measured.

    I doubt that this is a possible reason to different OFC values. That is, some of them is triggered to produce pulse current in self calibration, and the current will give different digital ground level from analog ground, which disturbs SELFCAL procedure.

    And I also notice that at 50SPS PGA=4, Buffer On, when input is shorted, there are 50 LSB noise in ADS1256 readings, about 18.4 bits noise free resolution, 2 bit lower than the 20.4 bits in table 3.

    Maybe it is the same reason with OFC errors.

    I will try tomorrow to modify the PCB ground planes to verify this.

    But I am still puzzelled why digital ground level will affect the operation of analog section. Are there any reasons in theory to interprete this.

  • Hi Chen,

    I'll try to address all of your questions...

    chen shi said:
    1. I use AIN2 as AINP and AIN1 as AINN, is that correct? They are adjacent inputs, datasheet page 14.

    This is fine...For self-calibration these inputs are disconnected and internal calibration signals are used for the inputs.

     

    chen shi said:
    2. I use 2 ADS1256s, which share SCLK, DIN, DOUT and VREF, other function pins DRDY and CS are seperatly controlled.
        The VREF circuit follows what in the datasheet fig. 16, except that 1 OPA350 drives 2 ADC parts, with 100+47uF titan capacitors, without 49.9ohm resistor. The circuit is the same with EVA board, but 1 OP drives 2 ADCs.
        Can they run correctly?

    This circuit is likely fine. I would consider adding some resistance between each ADC reference input and the OPA350 to "isolate" transient behavior from affecting all ADC reference inputs.

    Another thing to be aware of is that these large capacitors will take a long time to charge! The ADC's settling time may not be enough to account for the time required for the reference voltage to settle. You might consider using smaller reference capacitors to reduce this settling time.

     

    chen shi said:

    3. The init sequence 5 second after power up is:
            Wait for DRDY=0;
            Send Command RESET; wait for DRDY=0;
            Send Command SDATAC; wait for DRDY=0;
            Write Reg STATUS 0x02, for ACAL OFF, BUFFER ON.wait for DRDY=0;
            Write Reg MUX 0x21, for AINP=AIN2, AINN=AIN1;wait for DRDY=0; (AINP=AIN0, AINN=AIN1 for the second part)
            Write Reg ADCON 0x22, for SDCS OFF, PGA=4;wait for DRDY=0; (PGA=16 for the second part)
            Write Reg DRATE 0x63, for 50SPSwait for DRDY=0;
            Write Reg IO 0x01;wait for DRDY=0;
            Send Command SELFCAL;wait for DRDY=0;
        For each ADS1256, init sequence above is used. Is this sequence right?

    I don't see any issues with this configuration. One thing to be aware of is that enabling the buffer will limit the ADC's input range, and hence the reference voltage as well. If you're using a 2.5V reference this shouldn't be a problem; but you won't be able to use reference voltages greater than 3V with the buffer enabled.

     

    chen shi said:
    1. SELFCAL result changes.
        Each time when ADS1256s are powered up, and, after about 5 second, initialized one by one, I read back the OFC and FSC registers, they will change each time.
        I notice that FSC will change if OFC changes, and with same OFC values, FSC varies little, about 4-6 LSB.
        For the first part, I find some OFC values usually appear, say FFEF1F and FFEFBF, by chance, which affact the reading. Other values are near around these 2 values, but there are some other values, even they are not usually occur.
        At first, I doubt that the power up procedure will affect the self calibration, i.e. the reference voltage and supply voltage. So, I program the MCU to init the parts every 5 second following the above init sequence, and then read OFC and FSC registers, a long time after power on. The phenomena is same.
        And I also find that with time passed, after periodically init, OFC changes much, say from FFEF1F and FFEFBF to FFECA3 and FFED3F, about 636 LSB or 0x027C, but the difference of usually occuring values is about 160 LSB, or 0xA0.

    The calibration results will be different each time, but they should be close! Noise will always cause these values to change slightly. A change of 4-6 LSB is likely just noise and not too significant.

    For the larger changes in OFC and FSC there may be something else going on...You have all three ADCs sharing the same reference voltage and periodically re-initializing. It is possible for there to be some transient effects on the reference votlage that are affecting the calibration. To avoid this I would make sure each ADC had it's own RC filter prior to the reference input. Also, it would be best to initialize all ADCs once, allow a long delay time for the reference voltage to settle, then perform SELFCAL.

     

    chen shi said:
    2. ACAL turn on
        Then I turn on ACAL in STATUS register, after power up, both of them refuse to change DRATE to 4, it remains 30k, so I think other settings do not work too.
        Initialization every 5s also has no effect. Thet still output DRDY at 30kHz. In every 5s init, OFC and FSC also change, say OFC=FFFFFF or FFF120 or some other values, FFFFFF appears more, I think these values are of no sense since the DRATE is wrong.

    This sounds like an SPI communication problem. You should be able to change the data rate with ACAL enabled. Perhaps you're attempting to write to the ADC during the auto-calibration routine. Perhaps you can initialize the ADC with ACAL disabled. Once you've configured the ADC for the slower data rate, then you can enable ACAL.

     

    chen shi said:
    3. SELFCAL when short input terminals
        So, I have to use SELFCAL command to calibrate them, but this time I short the input terminals, because I think input signal will disturb the calibration procedure, the phenomena is similar. OFC changes to FFEF1F or FFEE7F. And I find that the reading is not near 0 or FFFFFF, it is FFFCxx. So calibration seems not work correctly.

    When you short the inputs, do you connect them to a valid common-mode voltage?

    Also, in the case where you apply the input signal, you would be better off running a system offset calibration (SYSOCAL), instead of a self calibration.

     

    chen shi said:
    4. SELFCAL on unused inputs
        Calibration is to connect input to VREF and 1/2VDD internally, input signals will not disturb calibration in theory. Even so, to avoid any disturbing, I use unused floating inputs for calibration, say AINP=AIN6 and AINN=AIN7, phenomena is similar, but OFC=FFEF1F occurs more.

    SELF calibration connects the inputs to the reference voltage. You should not see the inputs disturb the calibration as long as the input signals are not over-ranging the ADC. I don't think this behavior is very concerning.

     

    chen shi said:
    Why the OFC alters after SELFCAL command, and at the same time, short input readings are not near 0, even with floating input terminals? And why OFC havs some fixed values.
    Why the OFC changes so much, 636 LSB is not acceptable in my circuit.
    Why ACAL does not work? Are there any operations not correct in Init procedure?

    The OFC values will vary due to noise and the reference voltage. I think what maybe happening is that the reference voltage is still settling (or changing) during the calibration procedure.

     

    chen shi said:
        I have seperated analog and digital ground, and confirmed no jitter or digital current in analog ground. The deltaV between these two ground planes is lower than 100uV, measured by K2000 in fast mode with filter off.

    Where do you connect the analog and digital ground together? These grounds ought to be connected at the near the ADCs. Even though these grounds are within 100uV DC potential of each other, you could still have increased noise between these ground planes. Keeping a low impedance connection between AGND and DGND reduces this noise.

     

    chen shi said:
    And I was some confused by the datasheet. The information "the part will enter RDATAC state after power up" is not mentioned, and the formula (3) in page 24 has no clear statement, I cannot calculate the correct output from the formular with OFC and FSC. I would also like to suggest that an offical init procedure can be provided in the latest datasheet, I found so many problems about inits in the forum.

    These items have been noted. You are correct that the RDATAC must be sent prior to writing to the device registers. Also, I agree that the additional coefficients in the calibration formula are confusing!

     

    chen shi said:

    I notice in datasheet page28 that, digital and analog ground is recommended to be a single plane, and if use a split ground, difference between them is not allowed.

    This is unique for converters which have seperated defined ground pins.

    Internally, AGND and DGND are connected, however, they are pinned out separately to keep some of the digital noise out of the sensitive analog circuitry. To take advantage of this, digital components and traces should be "partitioned" from analog components and traces on the PCB layout. I would recommend using the same ground plane for AGND and DGND, to meet the requirement that AGND=DGND and also to avoid creating a ground loop.

     

    chen shi said:
    And I also notice that at 50SPS PGA=4, Buffer On, when input is shorted, there are 50 LSB noise in ADS1256 readings, about 18.4 bits noise free resolution, 2 bit lower than the 20.4 bits in table 3.

    The noise-free resolution table was calculated for a 2.5V reference. If you are using a difference reference voltage than the noise-free resolution needs to be adjusted for your reference voltage.

    For Vref = 2.5, DR = 50 SPS, and PGA = 4 V/V, you should be seeing about 13 codes/LSBs (peak to peak).

    Make sure you calculate the LSB size as 4*Vref/PGA (if you leave out the factor of "4", it might account for the missing 2 bits of resolution).

     

    Best Regards,
    Chris

  • Hi Chris

    --------------
    1. The powerup init is 5 seconds after powering up, I think the VREF with large capacitors should have been fully charged.
    2. The reference voltage is 2.5V, refered to ground, the common mode limit by input buffer should not be matter.
    3. After calibration, I short the input terminals, but find values far from 0, but FFFCxx. When I short the input terminals, they are at 1.5V, which is within the limit range of input buffer.
    --------------

    I have put digital and analog ground in a simple plane today.
    Because digital current produced by ADS1256 now will flow through some analog amplifiers and source, which are required to be very quiet and precision, I have to modify all of grounding points in a complex system to fit this change. It is really a hard work.

    Ground plane is seperated into several isolated parts, by graters, and then they are reconnected to suitable star points of their own.

    I find noise is slightly decresed, of about 1 bit lower, and when input terminals are shorted, the noise is within 25 LSB at 50SPS and PGA=4.

    Before I reconnect these isolated parts of ground plane, I measured resistance between digital and analog ground, there is more than 30k ohm. I think maybe they are not directly shorted in the chip, but only should have a certain voltage relationship, say, no difference between each other is required.

    So I am again confused. What is the reason of, in theory, why different voltage, including both DC and AC components, between this two ground pins will disturb the convertion procedure.

    Problem of self calibration is still not solved.

    There are still two fixed values for OFC, and one is 160 bit larger than another, the same as that before modified.
    I think FSC is correct, since when OFC is not changed, FSC will only change less than 6 bit. And when I write different DRATE to ADS1256, there are always 2 fixed OFC values corresponding to each data rate.

    I agree that voltage reference driving 2 ADCs without some isolation may affect the calibration, since there are 2, not only 1 part, running in one system. I suppose there must be something wrong in the init procedure.


    If the first part is in initialiing, but the second is still in converting, the second part will produce transcient state of the reference, and may cause a lot of current jitter in ground. Or the second part will contineous fan out its DRDY signal, which is coupled to the first part. I used double sides PCB, some digital signal traces have to be put in bottom layer, just under the first part.

    I have ever used LM336 to directly drive reference inputs to observe the reference voltage transcient in calibration procedure. In SELFOCAL, the reference voltage is not changed, but in in SELFGCAL, ref voltage will rise about 1mV, measured by K2000 in fast mode. So I suppose offset calibration is not seriously relied on reference voltage, but gain calibration is. Is this correct? If so, the reference transcient maybe is not the real reason. After reference input is driving by OPA350, as the buffer, with large capacitors, the problem remains.

    I think I should at least take the first ADC into standby mode by issuing STANDBY command, to force it to shutdown its digital circuit. When the second ADC is initializd, it is also set to standby, until the first one is waked up and initialized. Then two WAKEUP command are sent to two parts one after another to synchronize them. I will try it on Monday.

    I will try ACAL again, but I prefer the mannally calibration by issuing SELFCAL command after several WREG operations. It will save a lot of time, especially at low data rates.

    I add an input differential filter, two 360 ohm resistors with a 0.1uF capacitor, but after calibration, the reading will continously fall down, until it reaches a stable value, why? The capacitor is MKT.

    I would like to get more information about formular 3 in detail, to calculate the reading offset.

    And I would also like to verify if all operations to ADS1256, i.e. WREG, RREG, will make DRDY rising to high, or some commands do but others do not.

    Thanks alot.


  • Hi Chen,

    Regarding your last comments...

    chen shi said:
    1. The powerup init is 5 seconds after powering up, I think the VREF with large capacitors should have been fully charged.

    Five seconds should be sufficient for the OPA350 +  100uF capacitor to charge up to a 24-bit level, unless a large series resistor is placed prior to the capacitor.

     

    chen shi said:
    2. The reference voltage is 2.5V, refered to ground, the common mode limit by input buffer should not be matter.

    A 2.5V reference should be fine...Which ground is the reference referred to (AGND or DGND)?

     

    chen shi said:
    3. After calibration, I short the input terminals, but find values far from 0, but FFFCxx. When I short the input terminals, they are at 1.5V, which is within the limit range of input buffer.

    For SELFCAL, there is no need to short the inputs. You only need to do this for a system offset calibration.

    Also, I would not be as concerned by the absolute value of the OSC register result. However, inconsistent results are an issue!

    FFC00 would correspond to an offset of about -610uV. While this is large, I'm not sure if it is unreasonable (dividing by the gain of 4 V/V, results in an offset of only -152uV referred back to the input). Have you tried capturing data after calibration (keeping the inputs shorted)? If the calibration was effective, then the conversion results after calibration should be close to zero or "FFFFFF" (keep in mind the results are 2's compliment binary).

     

    chen shi said:
    I have put digital and analog ground in a simple plane today.
    Because digital current produced by ADS1256 now will flow through some analog amplifiers and source, which are required to be very quiet and precision, I have to modify all of grounding points in a complex system to fit this change. It is really a hard work.

    The digital currents should flow through the path of least impedance. Usually for higher frequency noise this means that the digital return currents will flow directly below the traces that sourced the current in the first place since this path is the least inductive. Therefore, if your layout partitioned analog and digital circuitry into difference regions on the PCB then analog and digital return currents should still remain separated, even when sharing the same ground plane.

     

    chen shi said:
    I have ever used LM336 to directly drive reference inputs to observe the reference voltage transcient in calibration procedure. In SELFOCAL, the reference voltage is not changed, but in in SELFGCAL, ref voltage will rise about 1mV, measured by K2000 in fast mode. So I suppose offset calibration is not seriously relied on reference voltage, but gain calibration is. Is this correct? If so, the reference transcient maybe is not the real reason. After reference input is driving by OPA350, as the buffer, with large capacitors, the problem remains.

    Correct. The conversion result is the ratio of the input voltage to the reference voltage. When the input signal is close to 0V, then the reference voltage does not have as much effect on the conversion result, as is the case when performing offset calibration (Still, it is important for the reference voltage to be settled to measure the offset voltage accurately). When performing gain calibration, the input signal is nearly equal to the reference voltage and the reference voltage has more impact on the ratio: "Vin/Vref".

     

    chen shi said:
    I will try ACAL again, but I prefer the mannally calibration by issuing SELFCAL command after several WREG operations. It will save a lot of time, especially at low data rates.

    FYI: If you are calibrating at a faster data rate and then taking measurements at a slower data rate, your calibration may no be valid at the slower data rate. It is best to calibrate at the data rate you're using for measurements, particularly with this device since the calibration coefficients scale differently with the data rate.

     

    chen shi said:
    I add an input differential filter, two 360 ohm resistors with a 0.1uF capacitor, but after calibration, the reading will continously fall down, until it reaches a stable value, why? The capacitor is MKT.

    How many conversion results did it require for the reading to stabilize? The ADC has a digital filter that is much like a moving average filter. In order for the reading to stabilize, you may need to take up to 6 readings, depending on the data rate (see table 15).

     

    chen shi said:
    I would like to get more information about formular 3 in detail, to calculate the reading offset.

    You can also calculate the reading offset by keeping OFC and FSC set to their ideal values. Then take measurement readings and compute the offset using the standard equations in table 16.

     

    chen shi said:
    And I would also like to verify if all operations to ADS1256, i.e. WREG, RREG, will make DRDY rising to high, or some commands do but others do not.

    The behavior of /DRDY after a command is not always consistent. Sometimes you can force /DRDY to return high by sending extra clocks. In general, you should only need to monitor for /DRDY falling edges to know when to retrieve measurement readings. Other than that, /DRDY is not needed for other operations.

     

    Best Regards,
    Chris

  • Hi Chris,

    Thank you for the fast responds.

    The series resistor to VREF input is 50 ohm, with 100uF capacitor, as what in Fig. 25. Even though there is a time constant, I have waited for minutes after powering up the chip, and then init it. OFC still change about 160 LSB larger or smaller among each powering up and initialization.

    The 2.5V reference is refered to AGND pin. There is now only one single ground plane, and this plane is star-point-grounded to gound plane for reference circuit, which involves the reference LM336 and buffer OPA350.
    LM336 has larger TC, but in my circuit, what I need is the proportion of voltage and current, voltage is measured by ADS1256, and current is produced by an DAC which shares this reference, the variation of Vref will induce no error.
    I monitor the Vref produced by LM336 all the time, it varies little, within 10uV in hours.

    In SELFCAL, there is no difference for OFC change problem, whether I do or do not short the input terminals.

    Offset is no matter, if it is a constant after every powerup and init, it is acceptable. But now it varies about 250LSB in reading and 160LSB in OFC, it seems something is wrong.
    After calibration, with input shorted, if OFC changes, the reading changes accordingly, and is far from zero of FFFFFF. I find the input shorted reading is always lower than zero, it is FFxxxx.

    The digital current is only produced by ADS1256, when I rearrange the gound plane, digital current directly flows to star point, and will not disturb other parts of analog amplifiers and sources.

    I am sure the reference voltage is fully settled to be very stable when init and calibration start. I suppose VREF is not the reason of variable OFC values after calibration, because I use high or low impedance reference circuit, there is no difference.

    I do calibrate the parts after I have configured its Buffer, DRATE and PGA.

    When two 360 ohm and one 0.1uF capcitor is used as a filter at input, I notice there may be about at least 5 second from the larger value appearing to it falling down to stable, at 50SPS, so there are about at least 250 readings. It seems not the behavior of the digital filter.

    What I think is to calculate actual zero reading by OFC to calibrate the OFC change mannually. So I have to use formula 3. I find in Table 8, alpha is a 24bit value of 4B0000. If OFC is FF0000 or FFFFFF, I cannot calculate different OFC/alpha values or different zero readings from the equation. Could you give me the method?
    I have tried to write zero to OFC and then issued SELFGCAL operation, so that OFC and FSC values are forced to be almost constant, but short input reading varies a lot too, after every time powerup and init.

    I have remove the 7.68M clock of the second ADS1256, and all of its digital control traces, physically, it is now in deep sleep. So there is only one ADS1256 is running. OFC still change a lot after every powerup or calibration.

    Are there anything reasonable for such strange phenomenan?
    I suppose there is some wrong in init and calibration procedure.
    Cound you suggest a standard procedure for me?

    If OFC value varies little, say lower than 10LSB, I can accept it and remove the error by CPU mannually.

    Thank you.

    Shichen
  • Hi Chen,

    Sorry for the delay...

    I ran some tests on the ADS1256EVM and observed that OFC only varied by about the same number of LSBs as the noise...

    For 30kSPS, PGA = 1 V/V, the noise is about 160 LSB, as shown below...

    I think what is happening is that you're running calibration at 30 kSPS and PGA = 1 V/V - This is the default setting for the ADS1256 after power up.

    When you reconfigure the data rate to 50 SPS and PGA =4 V/V, you should start to see OFC vary by only ~10 LSBs.

    FYI: I made up an Excel calculator that should help you decipher equation 3 in the data sheet. See attached:

    ADS1255-6 Codes & Calibration.xlsx

    I hope that helps!

    Best Regards,
    Chris

  • Hi Chris,

    I have checked my code, and now I only carry out SELFCAL every 5 seconds, after the 2 parts have been set as 50SPS.

    I also monitor the DRDYs signal of the 2 ADS1256s by oscilloscope. Before SELFCAL is execuated, I am sure the ADC is in the state of 50SPS, because the DRDY is at 50Hz.

    I see OFC values of FFEF1F and FFEFBF always appearing at the possibility of 90%, that is, in 10 times SELFCAL, there is only 1 result  which is not FFEF1F or FFEFBF. With more SELFCALs, I also see FFEF20, FFEF1E, FFEFC0 and FFEFBE, which are around these 2 values, only 1LSB.

    So I think it is not the sample noise, which leads to 2 very different OFC values. Otherwise, there will be several OFC values in a range of 160 LSBs.

    There is very few opportunity to see some more values between FFEF1F and FFEFBF, say FFEF5x or FFEF8x, or some other values, but such values actually exist. FFEE7F ever exists, it is A0 (160) LSBs lower than FFEF1F.

    I notice that one of the two ADS1256s has relatively fixed OFC (PGA=16), there are only 6 or less bits varied in OFC of FFFEC0 (it seems reasonable), but the other ADC (PGA=4) has two fixed OFC values, which are 4000LSB from 0, as mentioned above.

    I also notice that , after calibrations, even if with the OFC value is fixed, the ADC still gives different readings (about 50 LSB difference), when the two input terminal are directly shorted to a 1.5V voltage.

    I have checked the circuit and PCB, the two parts are nearly same. I exchange the SELFCAL calibration sequence of these 2, phenomena remains.

    I want to know if the SELFOCAL will be disturbed seriously by external factors, i.e. RF, or distortion of line voltage.

    I also find that resistors, between VREF input terminal and OPA350 output terminal, will generate obvious reference voltage change in gain calibration, up to 2mV higher, even with 100uF+47uF+0.1uF capacitors. When I remove the resistors, reference voltage is very stable in gain calibration.

    Now I can calculate offset reading by equation 3, thank you for your Excel calculator.

    Shichen

  • Hi Chen,

    It sounds like your OFC readings are fairly stable, except that you see two average offsets (like a bimodal distribution). I'm not exactly sure why you would see this...

    If you don't power down the device, but instead run additional SELFOCAL's back-to-back, do you still see the issue or is this behavior only occurring after power-cycling?

    Do you have a delay in your code to allow the ADS1256 to fully power-down before powering up again?
    The AVDD and DVDD capacitors still remain charge for some time after turning off the supply voltages. If you don't allow these capacitors to fully discharge before powering up again, you could be powering up the ADS1256 in an odd state that causes this and other odd behavior.

    Would you be able to share a schematic of you circuit?
    (It can be emailed to pa_deltasigma_apps@ti.com instead of posting it to the forum.)

    Regarding your other questions...

    chen shi said:
    I want to know if the SELFOCAL will be disturbed seriously by external factors, i.e. RF, or distortion of line voltage.

    It is possible for external factors to affect the offset... RF signals can be rectified by internal diodes and cause offsets. Typically, an IC is not too susceptible to RF by itself - usually an external coupling mechanism is required to direct the RF signal into the IC, such as a long cable or large loop area. Line cycle noise can affect ADC results, but the ADC (with decoupling) will be able to reject a fair amount of line cycle noise.

     

    chen shi said:
    I also find that resistors, between VREF input terminal and OPA350 output terminal, will generate obvious reference voltage change in gain calibration, up to 2mV higher, even with 100uF+47uF+0.1uF capacitors. When I remove the resistors, reference voltage is very stable in gain calibration.

    This makes sense to me...The reference inputs will have some amount of bias and transient currents. Series resistance placed on the reference inputs will cause some voltage drop to take place.

     

    Best Regards,
    Chris

  • Hi Chris,


    Thank you very much.


    The OFC have two relatively fixed values, FFEF1F and FFEFBF (A0 larger than FFEF1F), more than 90% appearance. I also see FFEE7F, A0 lower than FFEF1F, but it appears much little. Most of other values is between FFEF1F and FFEFBF. Values between FFEE7F and FFEF1F seldom appear, but they do exist. Maybe like a bimodal distribution, or maybe tri-modal?

    For example:

    FFEFBF +/-1LSB  about 45%

    some values like FFEF8x, 5% or more

    FFEF1F +/-1LSB  about 45%

    some values like FFEEAx, seldom appear, but actually exist

    FFEE7F   1% or less

    I will give a table of 100 OFC values after SELFCAL command tomorrow, at least 5 second interval between each calibration.


    I get these OFC values, whether after a only running SELFOCAL, SELFCAL, or after a manually self calibration after powering up. I find that once I have send SELFCAL or SELFOCAL command, OFC values always present such a distribution, no matter when the command reaches ADS1256.


    I think I have waited for an enough delay before powering up the part again, I have turned off the whole system, for at least 1 minute. After powering up again, OFC problem remains.


    When the 2 parts are powered up, I always run RESET command, I think this command will take the ADC from its odd state back to controlled state. Am I right?


    I also find only 1 ADS1256 has such problem, the second one has a relatively stable OFC value, in 16 LSB (I think it is correct). But even then, after a calibration, the second one will give different readings, 50 to 150 LSB variable, when the input pins are shorted. I mean, the readings are very stable, the noise is within 25 LSB, but the readings will change 50 to 150 LSB after each calibration.


    I will post my schematic tomorrow, it is in my office.
    Thanks again.

    Shichen

  • Hi Chen,

    I tried to replicate this behavior on the ADS1256EVM, but had not luck. After power cycling and configuring it to 50 SPS with PGA = 4 V/V, I read the same OFC result +/- 5 LSB consistently.

    I know that 5 seconds OUGHT to be sufficient for your power supply and reference to settle; however, as a sanity check try increasing this delay to see if your results change!

     

    Regarding your comments...

    chen shi said:
    When the 2 parts are powered up, I always run RESET command, I think this command will take the ADC from its odd state back to controlled state. Am I right?

    Not necessarily; the internal biasing may not always settle to intended values when powered-up after a partial power-down. However, if you have waited minutes for power-down than I think you've ruled this out. I would still give your system a few seconds to power down though.

    Also, it is good practice to run RESET after power up!

     

    chen shi said:
    I also find only 1 ADS1256 has such problem, the second one has a relatively stable OFC value, in 16 LSB (I think it is correct). But even then, after a calibration, the second one will give different readings, 50 to 150 LSB variable, when the input pins are shorted. I mean, the readings are very stable, the noise is within 25 LSB, but the readings will change 50 to 150 LSB after each calibration.

    Have you tired swapping the devices to see if the issue is related to the location of the ADC on your PCB? Maybe there is something related to layout that is difference between these locations on the PCB.

     

    Best Regards,
    Chris

  • Hi Chris,

    Thank you very much.

    Today, I turned on and off the system 100 times, with at least 10 second after turning off, before turning on again.

    I got 38 FFEF1Fs and 49 FFEFBFs. Other values are between them.

    FFEFBF-FFEF1F=A0=160LSB

    Then, I turn on the system, use keypad to manually operate SELFCAL command, every 10 seconds, for 120 times.

    I got 60 FFEFBFs, 35 FFF05Fs and 2 FFEF1Fs. Other values are scattered from FFEF1F to FFF05F.

    FFF05F-FFEFBF=A0=160LSB

    Yesterday, I got FFEFBF and FFEF1F.

    It semms sometimes when some strange condition changes, there will be some new values, say FFF05F (this is the first time it appears) for today, or FFEE7F for some days before, but they will often differ by 160LSB.

    The second ADC always gives stable OFC.

    I do swap the two ADCs.

    ADC1 from Channel1 to Channel2, ADC2 from Channel2 to Channel1. Now ADC1 is in Channel2 and ADC2 is in Channel1.

    And I get very large variable values of OFC from ADC2 in Channel1, say 0x300 to 0x500 LSB, and they are irregular. But the reading is very quiet with little noise.

    ADC1 gives very stable OFC within +/-5LSB in Channel2.

    So, you are right. Maybe something is wrong in PCB.

    But why, in one same PCB, something applying to ADC2 is much stronger than to ADC1. What is that?

    Discreteness among devices?

    The difference between two Channels.

    1. In Channel1, ADC is clocked by a 7.68M crystall with two 18pF capacitors, but in Channel2, ADC is clocked by D0 of the ADC in Channel1. I have observe these two clock signals, they are very clean, without spikes.

    2. In Channel1, ADC has 4 used input pins, or 2 pairs, AIN0 and ACOMMON, AIN1 and AIN2 (OFC problem happens here), ACOMMON is tied to ground, but in Channel2, ADC has only 2 input pins, or 1 pair, AIN0 and AIN1.

    3. In Channel1, PGA=4, but in Channel2, PGA=16. They are all configured to be in buffer on mode, 50sps.

     I had ever physically cut off the clock, SCLK, CS, DIN, DOUT and DRDY trace of ADC in Channel2 to force it into deep sleep, ADC in Channel1 still gives variable OFC.

    Today I tried plan B.

    I force the OFC register to be zero, and then issue SELFGCAL command to calibrate gain.

    Now I get fixed OFC (of course), and a fixed FSC within 16 LSB (it is enough), input shorted readings after every time calibration is almost fixed now, there will be 100 LSB (about 16uV) change from powering up to warmed up in 1 minute or 2, I think it is thermal potential.

    I know actual offset voltage will not be zero, but I can change OFC register until the shorted input reading reaches zero. And then gain calibration.

    I will store this OFC value in ROM, and write it to ADC after it is powered up.

    Before plan B, I think I should realize the reason of variable OFC. There may be some fatal bugs in circuit or code if OFC problem remains.

    So I want to know what will affect offset calibration process, including external and internal factors, i.e. power supply, reference (I donnot think it will work), code, sequence, or other things?

    Since I have got very stable readings, they present little noise, I would like to know if there are something which only affects offset calibration result but does not affect stability of readings.

    In origin PCB, digital signal traces of ADC in Channel2 is in the bottom layer under the ADC in Channel1, but now I have cut them totally off from the PCB by removing the copper traces, and connect them to ADC in Channel2 again by jumper wires, 5mm from bottom suface of PCB, so they will not disturb Channel1 anymore.

    I have removed two 50 ohm resistors between OPA350 output pin to ADS1256s' Vref pins. I feel these resistor will eliminate the advantage of OPA350's low output impedance in high frequeny.

    I notice the digital input of ADS1256 is 5V tolerant, I use 5V control signal with a 100 ohm resistor to each digital input pin. Is that matter?

    Analog 5V is supplied by a 78M05, digital 3.3V is from a LM1117-3.3, each ADC has individual 2 set of decoupling capacitors, 10uF and 0.1uF ceramic, for 5V and 3.3V, seperately. Is it enough for ADS1256 to run a correct offset calibration?

    Shichen

  • Hi Chen,

    This could be causing a serious problem...

    chen shi said:

    I notice the digital input of ADS1256 is 5V tolerant, I use 5V control signal with a 100 ohm resistor to each digital input pin. Is that matter?

    Analog 5V is supplied by a 78M05, digital 3.3V is from a LM1117-3.3,

    If DVDD is set to 3.3V and you're controlling the device with 5V logic, a number of different problems can occur...

    1. The digital input pin is diode connected to DVDD; therefore, if the digital input voltage is 5V and the DVDD supply is 3.3V, then this diode is forward biased and likely drawing a large current (between 10-17 mA). This input current exceeds the absolute maximum ratings of the ADS1256 and could permanently damage the device, especially, if this occurring on more than one digital input pin.
    2. Additionally, this current will heat the ADS1256 and could explain the thermal potential you mentioned...
      chen shi said:
      Now I get fixed OFC (of course), and a fixed FSC within 16 LSB (it is enough), input shorted readings after every time calibration is almost fixed now, there will be 100 LSB (about 16uV) change from powering up to warmed up in 1 minute or 2, I think it is thermal potential.
    3. The digital outputs of the ADS1256 will only drive up to the DVDD voltage; therefore, it is also possible that the MCU may misread a "1" for a "0", because 3.3V is in the marginal voltage range of the 5V logic.

    I recommend correcting this issue first to see if it also resolves the self-offset calibration issue. If you cannot adjust the MCU's logic level, than you may need to add a level-shifter to your PCB, because the ADS1256's DVDD power supply cannot exceed 3.6V.

    Best Regards,
    Chris

  • Hi Chris,

    I find in datasheet, the digital input is 5V tolerent, how to understand this "tolerent"? If there is no "tolerent" description, I think I have used a level shifter in this interface.

    The digital output pins drives a level shifter 74LVC4245, which transmit the level to 5V, and then into optocouplers, before it reaches MCU. I have monitor the signal level, it is 5V high and 0V low.

    If there is clamp current at input pins drawn by diodes up to 10mA, it is reasonable, because I have seen offset drift out of ordinary in the first 5 minutes after powering up, far from specifications listed in datasheet. I will try to arrange another PCB to add a shifter.

    ----------------------------------------------------------------------

    I also notice that, in most applications, D0 is not used as clock output.

    In my application, the first ADC's D0 drives the second one's clkin pin, the first ADC is clocked by a cystall. Only the first ADC has OFC problem, the second one has stable OFC.

    Does D0 affect something? In your Evaluation Board, have you set CLK1:CLK0 in ADCON register as 00 to make clock out off? I think to simulate the OFC problem, there should be a load at D0 to draw enough current as what CLKIN pin of ADS1256 will do, so this current may affect OFC resister in calibration, when D0 is used as clock output.

    I find some description about ADS1255/56 (not from TI) strongly recommends stopping D0 as clock output if not necessary, is it a preferable choice?

    I also find in other ADC's datasheet, say AD7712-2, says that the clock out function will degrade the performance, does it also apply to ADS1256?

    I will try to stop this clock out first, and clock the second one by a crystall to see what happens.

    Thank you.

    Shichen

  • Hi Chen,

    chen shi said:
    I find in datasheet, the digital input is 5V tolerent, how to understand this "tolerent"? If there is no "tolerent" description, I think I have used a level shifter in this interface.

    I'm sorry, you're correct about the 5V tolerant digital inputs... I'm use to going by the DVDD supply limits as the digital interface limits as well. This device is an exception, you can supply a 5V input signal even when DVDD is 3.3V. - In this case, this should not cause a large current flow into the device!

    It is good that you level shift the digital output signals from 3.3V to 5V logic!

     

    chen shi said:

    Does D0 affect something? In your Evaluation Board, have you set CLK1:CLK0 in ADCON register as 00 to make clock out off? I think to simulate the OFC problem, there should be a load at D0 to draw enough current as what CLKIN pin of ADS1256 will do, so this current may affect OFC resister in calibration, when D0 is used as clock output.

    I find some description about ADS1255/56 (not from TI) strongly recommends stopping D0 as clock output if not necessary, is it a preferable choice?

    I also find in other ADC's datasheet, say AD7712-2, says that the clock out function will degrade the performance, does it also apply to ADS1256?

    The CLKIN pin should be a high impedance input that does not draw much current. By default, the CLKOUT output is enabled on the ADS1256.

    I haven't seen a difference in the OFC calibration register results when turning CLKOUT on or off. I don't think enabling this function should have much effect on the OFC result. Depending on the layout, it is always possible for clock signals to capacitively couple into other signals; however, I have not heard about CLKOUT causing any problems.

     

    Are they any other devices or large currents on your PCB that might explain the need to wait 1-2 minutes for the board to warm-up?

     

    Best Regards,
    Chris