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DAC8718 power supply problem.

Other Parts Discussed in Thread: DAC8718, DAC8718EVM

Hello, I am testing DA8718.

I got a problem that DAC outputs offset voltage(about 8V) .

When I supply each +5V and+-12V at the different time, separately, the DAC outputs right voltage in +-10V range (reference voltage 3V).

But When I suppl volage +5V and +-12V to DAC  at the same time, DAC outputs wrong voltage.

Then, I supplied the voltage as following steps.

1) I disconnect the +5V line. And remain +-12V at the same time.

2) I reconnect the +5V line.

In this case, the DAC outputs right voltage well.

I read the datasheet page 44. I did pull up the LDAC, RST, CLEAR, etc.

What do I initialize for DAC8718? 

Thanks for reading.

  • Hi Hahmin,

    Can you confirm for me what the pins that you are supplying +5 V and +12 V are?

    I assume:

    AVDD =  + 12 V

    IOVDD and DVDD = + 5 V

    If this is the case I think you may have missed the paragraph on Power-on Reset Sequencing on page 44.

    You need to provide IOVDD and DVDD before you provide AVDD. Otherwise the device will not power-on correctly. This is because the device includes an OTP (One Time Programmable) register that is set by IOVDD and DVDD at power-on. Bringing up AVDD first, or even at the same time can cause all sorts of problems, including offset errors. Please verify that you are following this power on sequencing.

  • Hello Eugenio,

    Thank you for the quick reply.

    I am supplying  +3.3V to IOVDD and DVDD. And I am supplying +12V to AVDD. And I am supplying -12V to AVSS.

    You said that I  need to provide  OVDD and DVDD before you provide AVDD.  

    But I got a right voltage output when I provide AVDD  before OVDD and DVDD.

    I attached my schematic as follows:

    Is It the right schematic? If yes, How do I solve this problem?  Do I supply the 3.3V before +-12V ?

    Thank you for reading. 

  • Hi Hahmin,

    hahmin jung said:
    Do I supply the 3.3V before +-12V ?

    Yes. Please provide the +3.3 V supply before the +/- 12 V. After this supply the reference voltage. This will allow the DAC to power-on correctly.

    hahmin jung said:
    But I got a right voltage output when I provide AVDD  before OVDD and DVDD.

    This is certainly possible. The biggest problem with violating the power-on reset sequence is that different devices can behave differently. It is possible for a device to power-on correctly during an invalid power-on reset sequence, but another device may not. This is why it is so important to implement it.

    The schematic that you show looks good to me. Thank you for sharing it, it really speeds up the debugging process. I do have a question. Why are you connecting a capacitor to the Vmon pin?

    Let's see if the power-on reset sequence solves the problem, otherwise we can take a look at a few more things.

  • Hello Eugenio

    I read your reply.

    I connected the capacitor to the Vmon pin. I thought that the capacitor help to through noise from DAC to AGND when I check the analog signal from DAC. 

    I am still testing the DAC. Maybe I have to remake a PCB for keeping power on sequence that provide 3.3V firstly than +-12V .

    For example, If I use EV-board for DAC8718 by TI, I have to provide 3.3V firstly than +-12V ? 

    I didn't find a circuit for DAC power on sequence.

    Thanks for reading.

  • How are you currently supplying the +3.3 V and the ±12 V? On the DAC8718EVM you can supply them separately, by turning on the supplies at different times. You could use on your PCB a supply chip with an enable pin that is connected to a supply detect circuit.
  • Hello Eugenio

    I am supplying the +3.3V and +-12V at the same time from POWER BOARD.

    If I have to test the DAC8718EVM, Do I have to provide +3.3V firstly than +-12V ?

    If this method that supplying 3.3V than +-12V is true, I will have to modify DAC BOARD by me.

    Thanks for reading, replying, and helping.

    Thank you, 

  • Hi Hahmin,

    hahmin jung said:
    Do I have to provide +3.3V firstly than +-12V ?

    Yes. You have to provide +3.3 V first, then ±12 V in order to be able to test the DAC8718EVM.

    hahmin jung said:
    If this method that supplying 3.3V than +-12V is true, I will have to modify DAC BOARD by me.

    It is a requirement as started in page 44 of the datasheet. Usually DACs that require more than one supply, have a certain power-on reset sequence to follow.

  • Hi, Eugenio

    I understand that +-12V level is provided to AVdd and AVss after
    LDAC, CLR, RST, CS, RSTSEL, IOVdd, DVdd are supplied to 3.3V level.
    And The REF-x pins must be applied last. The supplying sequence is as follows:

    3.3V ___------------
    +12V_______--------
    -12V _______---------
    REF _________------

    Can you introduce an example to supply as upper sequence?

    And what is the time between 3.3V and +12V? (delay time, about 1 sec ?)

    Thank you for reading,

  • hahmin jung said:
    Can you introduce an example to supply as upper sequence?

    I am not sure what kind of example you expect for this. I think you understand the sequence necessary.

    hahmin jung said:
    And what is the time between 3.3V and +12V? (delay time, about 1 sec ?)

    The next supply can start ramping as soon as the previous supply has reached full value. In other words, the delay is only dependent on how fast your previous supply the ramp is.

  • Hello, Eugenio

    I have a last question.

    If the device includes an OTP (One Time Programmable) register, can I clear the register when I provide

    wrong +- voltages ?

    If there is no way to clear, I have to use mechanical relay for supplying +- voltages.

    Anyway, Thank you for replying to help me.

    Take care~.
  • Hi Eugenio and Hahmin,

    I can not see if there was a follow up on the last question from Hahmin. Does the chip foresee a SW reset or sequence that would bring it from this - locked- state?

    Thank you,

    Uros
  • Hi Hahmin,
    On page 44 of the datasheet, we recommend a power on sequence.
    Can you confirm that you are adhering to this sequence?

    "For proper power-on initialization of the device, IOVDD and the digital pins must be applied before or at the same
    time as DVDD. If possible, it is preferred that IOVDD and DVDD can be connected together in order to simplify the
    supply sequencing requirements. Pull-up resistors should go to either supply. AVDD should be applied after the
    digital supplies (IOVDD and DVDD) and digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL). AVSS can
    be applied at the same time as or after AVDD. The REF-x pins must be applied last."

    Best Regards,
    Rahul Prakash
  • Hi Rahul,

     I can confirm we do NOT comply with the specified power up sequence. For this reason I am asking if there is any other way to recover the chip from a faulty state other than redesigning, relayouting the PCB in our case. Is there any "magical" sequence of reset, clear  wakeup,... control pins which would do the job?

    I believe this was the last question in the thread but there was no answer - so I reasked.

    Thank you for all your help,

    Uros 

  • Hi Uros,
    I have checked this with our design team.
    Unfortunately, the only way to recover from this faulty state is to power up the DAC with correct power on sequence which is mentioned in the datasheet.

    Best Regards,
    Rahul Prakash
  • Hi Eugenio
    I meet the same problem very like as Hahmin. The power up sequence is not right as Page 44 said . I write the value to dac-0 but all the Vouts ouput a wrong voltage.But it is strange that i could write/read 0x03、0x04 (offset register )etc. correctly.
    I have a question about Page 44 paragraph:
    It is that LDAC, CLR, RST, CS, RSTSEL need to pull up to IOVDD. But if I need LDAC, USB/BT, RSTSEL, WAKEUP to be logic low, can I pull them down to GND before the power up?
    Thank you !!
  • Hi Rahul
    How long delay should I take for the each voltage?Thanks
  • Hello,

    LDAC, CLR, RST, and CS can be dynamic pins during actual use of the device - however I believe the datasheet is recommending that these be tied high during power up such that no unexpected behavior occurs during power-up. For example maybe there is noise from the MCU at power up on the SDI pin and this data is errantly latched and creates an unexpected voltage at the output.

    Other pins are latched at power-up, like USB/BT and RSTSEL. These pins should be tied to their desired potential at power-up based on the functionality of interest. So if the pin should be tied low for your function, it should be tied low during power up. Use of LDAC is optional, so you could have this tied to GND at power-up if you'd like.
  • Thank you for the quickly reply. Another is that what's the exact delay should I take for the right power up sequence?
  • Hello,

    Power-on sequencing isn't a trimmed property of these devices - so there is no "exact" timing. In fact, the DVDD/IOVDD rails don't even really need to completely ramp and settle before the analog rails start to come up, it just needs to cross some threshold which triggers the POR circuit to start the OTP read. Most likely this occurs around 2.7V or earlier, if the analog rails start to ramp around this time I think you should be okay.

  • Thank you ! I'll try as you suggested,thank you.

  • Hi duke,

    I've done some changes about the circuit. The test result is shown as below:

    1.Now I used three power +3.3VDC,+8VDC and +5VDC .They are all controlled by manual power supply. IOVDD and DVDD ard tied together to 3.3V and are power up at first.Then manual power the AVDD with +8VDC. At last the +5VDC for Vref. AVSS is tied to AGND. AGND and DGND are tied together.  

    2.USB/BT is tied to GND and RSTSEL is tied to +3.3V.That means we use unipolar supply and choose the straight binary code.If we do reset operation, all the dout is NOT half full scale voltage as datasheet said.

    3.All the address from 0x10 to 0x1F can be read and write correctly. The SPI read operation timing is matched with datasheet said.

    4.The DAC-X register can not be read correct. But when we write data to these registers, the D-OUT will be changed. The SPI read operation is not right. 

    Can you help me  analyse the situation?  

    Thanks !

  • HI Duke,
    There are some question about I did another test on bipolar supply.
    The IOVDD and DVDD tied together to +3.3VDC is powered up first. Then power +-16VDC to AVDD/AVSS(AVDD powered first). At last power +5VDC to Vref. RSTSEL is tied to +3.3V,USB is tied to GND both through a 1kohm resistor.
    After reset, all Vout are about +5.8VDC, NOT 0Vdc. I wrote 0xFFFF to 0x08 register ,Vout0 is still about +5.8VDC. I wrote 0x0000 to the 0x08 register , Vout0 changes about to -16VDC(full scale of minus). The value of OFFSET register is default, I did NOT operate it.
    So what should do to modify the Vout0 to plus scale of AVDD as your suggest, thank you!
  • Hello,

    I am on business travel right now, so I apologize for any late responses going forward. If needed, I will ask someone else from my team to help support this thread in my absence.

    The best thing, in my opinion, to debug both issues would be to see oscilloscope captures of:

    • The SPI read sequences that are not successful
    • The DVDD / IOVDD / AVDD / AVSS supply ramps

    With these captures we can study the wave-forms and try to give you some advice.

  • Hi duke.

    Thank you for help.

    1.The capture below is shown the timing of read 0x08 register. It is suppose to read back the default value 0x8000,but return 0x00. And now the VOUT0  is about +5V, not the defalut value 0V.

    2. The power supply is controlled by manual operation. The sequence is IOVDD/DVDD(+3.3V), then AVDD/AVSS (+-16V), Vref(+5V). Delay betwee each is about 5 seconds or more. The supply ramp capture are shown below.

    V ref  +5V

    AVDD +16V

    AVSS -16V

    IOVDD +3V3

    Thanks again !

    BR

  • Hi Duke,

    I think perhaps I've found the problem.
    I turned the Vref to +3V, and keep other power supply the same as before(IOVDD=DVDD=+3.3V,AVDD=+16V,AVSS=-16V). Then the default value of VOUT=0V, and the span is good when I wrote the full scale value to the register(+-9V as datasheet issued).
    Maybe I should make Vref not higher than DVDD? I am not sure about that , because it's hard to disconnect DVDD from +3.3V on my pcb board.
    Can you give me some advice?
    Thank you!

    BR
  • Howdy,

    Kevin is currently traveling, but I should be able to assist you with your question.  Please note that the device will only operate as specified in the datasheet only if the conditions don't violate any limits listed in the "absolute maximum ratings" table.  This table indicates that the RefA/B pins should only operate within (-0.3 to DVDD), therefore the reference voltage should never exceed DVDD. Exceeding DVDD will activate internal ESD structures, which will cause faulty behaviour  and may possibly damage the device.

    Best Regards,

    Matt

  • Hi Matt

    I think it is the problem of my design.

    Thank you for your surpport ! And BR  to  your team!

    Yours

    XY