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ADS 1278 TDM mode configuartion

Tejas s j
Intellectual 395 points
Other Parts Discussed in Thread: ADS1278

I have interfaced ADS1278 to an FPGA,  Altera cyclone III. The Discrete mode operation has been verified for all the eight channels, but the TDM mode operation is not working.

I am operating in Low-speed mode and FORMAT [0:2] = [000]. All the !PWDN pin are tied to +3.3V. 

CLK = 25.6 MHz ,  therfore the sampling rate becomes 10 KSPS.

SCLK = 12.8 MHz

The procedure followed is :

After the DRDY pin goes LOW, the FPGA sends 192 pulses of SCLK to the ADS1278. The output from DOUT1 is serially read by FPGA. 

This gives a random output signal in all the channels. Is there something doing worng in whole process while reading in TDM mode?

  • 0
    TI__Guru 57336 points

    Hello Tejas,

    It sounds like you are following the correct procedure for reading data in TDM mode, but we will have to double-check your SPI timing specs to make sure we're not violating anything on page 8 of the datasheet. Could you share a screenshot showing /DRDY, DOUT, and SCLK?

    Also, how are the inputs of the ADC configured? Are you giving a known input signal to the device or shorting the inputs?

    Best Regards,

  • 0 in reply to Ryan Andrews
    Intellectual 395 points
    Hello Ryan,

    The input signal given to ADC is a sine wave , it is observed that the digital output is correct for the the DISCRETE MODE but the TDM mode is giving a random digital output.
    I am guessing that my FPGA program for reading inTDM mode may be the problem.
  • 0
    Intellectual 395 points
    Hello Ryan,

    I was able to verify TDM mode. I changed the architecture of my FPGA program. I still have a question,
    Will providing a free running SCLK or 192 SCLK pulses after detecting the LOW pulse on DRDY pin make any difference in DOUT from ADC?