I'm a little bit confused as to what SCLK frequency in my SPI protocol I should use.
I was planning to use f_CLK = 512kHz, and DR = 125SPS or 250SPS. That means that my SCLK could be about 39kHz without any problems.
I read in the datasheet that SCLK can only be 2*f_CLK for register reading and writing operations. If I intend to only do such things before starting to send RDATAC and pulling START high (meaning, doing it only in the very initial setup phase), then 39kHz is fine?
Also, for reading data, I'm basically doing the following:
while True:
if not_DRDY == 0:
wait for 1ms
x = readbytes(3) //status bits
y = readbytes(3) // CH1
z = readbytes (3) // CH2
VCH1 = (y[0]<<16) + (y[1]<<8) + y[2]
VCH2 = (z[0]<<16) + (z[1]<<8) + z[2]
V1 = VCH1*2.42/(2^23 -1)
V2 = VCH2*2.42/(2^23 -1)
-----------------------------------------
Is this correct?
