Hello!
Looking at the Table7 of the IC datasheet, I'm trying to figure out what's the reason behind settling time for 64ksps and 32ksps modes being, accordingly, 152 and 296 fCLK cycles.
I do understand there's, apparently, 4 tCLK delay to startup conversions and 4 tCLK delay to output conversion result into shift register. So we're left with 144 and 288 fCLK cycles.
fMOD = fCLK/2, so it leaves 72 and 144 fMOD cycles.
There is also 3 samples settling time of the sinc LPF, and there is decimation ratio (1 for 64ksps, 2 for 32ksps). So dividing by 3 and 6, I end up with 24 fMOD cycles per single sample. Which I find weird, because with DR of 1 and 2, the ADC works in 16 bit mode.
What's more, after the initial start delay, single sample is obviously taken every 16 fMOD cycles, or else it wouldn't manage to meet 64 and 32 ksps data rates.
The question arises - why is the start settling time based off 24 bit sampling times in 16 bit sampling modes?
The given calculations make perfect sense to me for the slower, 24 bit modes, where I also get 24 fMOD cycles per sample.
