Hi,
We have 7 devices on a SPI interface which is controlled by an MSP430. From the data sheet we expected that when the data ready output was asserted (low) then this would be cleared by the SCLK only for the ADC with the chip select active. This is not what we observe. The DRDY is returned high for all the ADCs on the bus at the first SCLK even though the chip select is high for six of them.
I have attached a couple of logic analyser plots showing this behaviour. These show the SCLK and DRDY and CS for three of the ADCs. There is also a signal named DRDY_COOLANT_NAND that indicates to the MSP430 that DRDY is present for the ADC selected. As you can see, this only occurs for the first one that is read.
We have the START tied high so that the ADCs are free running and CLK tied low so that they are clocked internally. The sampling rate is 20 samples per second and we are trying to read them all in a group every 250ms.