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ADS1278 FRAME-SYNC FORMAT TIMING

Other Parts Discussed in Thread: ADS1278

When I read the datasheet about Frame-SYNC FORMAT TIMING. I realize the time of Falling edge of CLK to Falling edge of SCLK (tCS).

They say: tCS is (-0.25,+0.25)tCLK. And SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK.

So I want to know whether I must keep every Falling edge of  CLK to Falling edge of SCLK meet the tCK, or I just meet the Timing when the FSYNC goes HIGH.

Because my project has some problem. I give the ADS1278  the same sine via OP, but when I see the data from MTALAB, there is something wrong.

Someone told to me that my timing had some problem. I want someone  to give me kindly advise about where I should notice when I use the ADS1278. 

Thinks for listening.

  • Hello,

    Thanks for your question and welcome to our forum!

    First, the timing requirement, tCS, must always be met, regardless of the status of FSYNC. FSYNC simply indicates the beginning and end of each frame of data - CLK and SCLK falling edges must be aligned to within +/-0.25tCLK to prevent the data from being corrupted.

    Second, SCLK/CLK ratios of 1/2^n will give you the best performance, but this is not a requirement. As long as you satisfy the other timing specifications, you will still achieve the performance described in the datasheet.

    Best Regards,