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Questions about ADS1299

Other Parts Discussed in Thread: ADS1299

Hi,

I'm working on ADS1299 driver. And I can read ID and initialize the ADS1299. But the problem is that the DRDY signal is generated every 10ms. I checked it by oscilliscope. I think the minimum sampling rate is 250Hz, which means DRDY signal should be found every 4ms. 

Why can it get 10ms interval?

Best Regards,

  • Hey Mian,

    How is the clock being provided by the ADS1299?

    Regards,
    Brian Pisani
  • Hi Brian,

    I'm using internal clock which is 2.048MHz. And it is configured by hardware (CLKSEL pin is pulled up).

    Best Regards,
  • Hey Mian,

    Is it possible for you to probe the clock output? if the CLK pin is floating, can you set bit 5 of the CONFIG1 register, probe it, and tell me at what frequency the clock is oscillating?

    Brian Pisani
  • Hi Brian,

    I configured the CONFIG1 register as 0xB6, and measured the frequency output on the CLK pin. It's about 500ns interval, which means 2MHz.

    It's correct, right?

    Is there anything else that I can check?

    Thanks a lot.


    Best Regards,
  • Hey Mian,

    Yes that is the correct frequency. The data rate is divided from that clock directly so it seems that if that clock is correct that the data rate should also be correct. Does the problem persist for different data rates? Would you mind sending me a screen capture of your oscilloscope displaying the issue?

    Regards,
    Brian Pisani
  • Hi Brian,

    I tried the different sampling rate. For example, by default the sampling rate should be 250Hz, which means we should have 4ms interval. But in fact I have about 16ms interval. When I configured the sampling rate as 1024Hz, which means we should have 1ms interval. At this time in fact I have about 4ms interval.

    Here is the pic based on 250Hz:

    Here is the pic based on 1024Hz:

    And the yellow should be DRDY signal while the green should be CS signal.

    Thank you for your great support.

    Best Regards,

  • Hey Mian,

    It seems like the DRDY is happening 4x slower than what you configure. Is SCLK doing anything in between the DRDY pulses? If not, have you tested this with another board?

    Regards,
    Brian Pisani
  • Hi Brian,

    I have tested it with another board, and it is the same thing. I'm thinking if it is a software issue? Here is what I did:

    When the board boots up, and I reset the ADS1299, and then I can read ID correctly. After that I configured the register by sending the following commands:
    0x41, 0x11, 0x96, 0xC0, 0xEC, 0x00,
    0x80, 0x60, 0x00, 0x00, 0x80, 0x80,
    0x80, 0x80, 0x02, 0x02, 0x00, 0x00,
    0x00, 0x00

    And then, I configured the GPIO by sending the following commands:
    0x54, 0x04, 0x0F, 0x20, 0x00, 0x00, 0x00


    After all above, I send WAKEUP command(0x02) and Start command(0x08).

    That's all what I did so far. Just show more details here and hope you could give me some suggestions or hints.

    Thank you for your greate help.



    Best Regards,
  • Hey Mian,

    I'm not sure I understand exactly what commands you're giving. Could you just tell me which registers you write and with what values? I can only think of one reason that DRDY would be 1/4 the normal frequency. Is the device configured in single-shot mode and are you controlling conversions wither by pulsing the START pin or sending the START command for every sample?

    Regards,
    Brian Pisani