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ADS1278 unexpected behavior

Gaston Schelotto
Expert 2820 points
Other Parts Discussed in Thread: ADS1278

Hi,

Years ago I developed an acquisition system based on ADS1278 and C6747 using this configuration:

  • Frame-Sync format - Discrete DOUT mode
  • High-Speed mode
  • Discrete Data Output Mode
  • CLK/SCLK range [11MHz to 18MHz]
  • 8 input channels enabled

For each input channel, it was designed to acquire a low frequency sine waveform (40Hz to 70Hz) in 10240 samples through ADS1278 Frame-Sync Serial Interface and McASP+EDMA subsystem on the C6747. For example, the 10 cycles of a 50Hz input waveform comprises 10240 samples as shown (CLK/SCLK=13.107200MHz)

So far so good, 13.107200MHz / 256 = 51200SPS that fits with the expected results (51200SPS / 10240 samples = 5Hz, the window's size)

However, if I change the input frequency to 51Hz I get a distorted waveform (CLK/SCLK remains fixed to 13.107200MHz)

Now if I set the input frequency to 55Hz (a multiple of 5) everything is okay (noticed that we have 11 entire cycles instead 10)

It seems I cannot introduce an input waveform different of a multiple of 5Hz. Why? Can anybody explain me what's going on? I'd appreciate any help.

regards,
gaston

  • 0
    TI__Guru 57346 points
    Hello Gaston,

    Are you interrupting FSYNC in anyway? FSYNC should run continuously based on the expected output data rate of the ADS1278.

    In the second figure, it almost looks like you have introduced a short delay and therefore you missed some samples. The x-axis is plotted in "Samples," so there is no "gap" in the waveform, but they do not appear to be contiguous points.

    Best Regards,
  • 0 in reply to Ryan Andrews
    Expert 2820 points

    Hi Ryan,

    Ryan Andrews said:
    Are you interrupting FSYNC in anyway?

    Yes, FSYNC (pin 29) is tied to McASP AFSR1 output of C6747and SYNC (pin 11) is tied to 3.3Vdc.

    Here's the FSYNC (channel 1) running continuously and DOUT1 (channel 2)

    Ryan Andrews said:
    In the second figure, it almost looks like you have introduced a short delay and therefore you missed some samples.

    Yes, is strange. I'm not introducing any delay in the acquisition process. All is performed by EDMA3 and McASP peripherals (with double buffer ping-pong implementation). I still don't understand the second figure.

    regards,
    gaston

  • 0 in reply to Ryan Andrews
    Expert 2820 points

    Ryan, It seems I'm facing a synchronization issue between EDMA3 transfer and CCS graph display through XDS510-JTAG. The ADS1278 seems to be okay so let me investigate further before close this post.

    regards,
    gaston

  • 0 in reply to Gaston Schelotto
    TI__Guru 57346 points

    Gaston,

    Thanks for the update. Let us know if you need further assistance with this issue.


    Regards,